CW25 Software User Manual
Page
12 of 50
Rev 03
Date: 06/16/08
Copyright ©2007 NavSync Ltd.All Rights Reserved
Specifications subject to change without notice.
4.2 RF Signals
RF_IN
Type: RF
Direction: Input
Pin: 24
The RF input signal. This attaches to the GPS antenna. Standard RF design rules must be
used when tracking to this signal. This signal has an RF blocked connection to the
ANT_SUPPLY signal. This is the same signal presented on the RF connector on the CW25.
Only one antenna connection should be made. If the RF connector is to be used, then there
should be no connection, even an unconnected pad, to this castellation.
TRIM
Type: RF
Direction: Input
Pin: 12
This signal trims the output frequency of the VCTCXO. This signal is normally left open.
When floating, this signal is biased to the control voltage of the VCTCXO. Any noise injected
into this signal will severely compromise the performance of the CW25. This signal should
only be used in conjunction with specific application notes.
EXT_CLK
Type: RF
Direction: Input
Pin: 7
This input is the external clock input. This signal is to be used only in special builds of the
CS25 that are not fitted with an internal VCTCXO. For the normal build, containing the
VCTCXO, do not connect this input. The external clock is a 20 MHz clipped
sinewave input with an amplitude between 1V and 3V peak to peak. The return path for
this signal is RF_GND.
4.3 Emulation/Test Signals
TDI
Type: Test
Direction: Input
Pin: 14
The Test Data In signal. This is the standard JTAG test data input.
The signal return path is DIG_GND.
TDO
Type: Test
Direction: Output
Pin: 13
The Test Data Out signal. This is the standard JTAG test data output.
The signal return path is DIG_GND.
TCK
Type: Test
Direction: Input
Pin: 20
The Test Clock signal. This is the standard JTAG test clock input.
The signal return path is DIG_GND.
TMS
Type: Test
Direction: Input
Pin: 22
The Test Mode Select signal. This is the standard JTAG test mode input.
The signal return path is DIG_GND.
JTAGSEL/RTCK
Type: Test
Direction: Input/Output
Pin: 21
This is a dual function signal. When the NPOR signal is asserted (low), this signal is an input
and selects the function of the JTAG interface. When high, JTAG emulation into the embedded
ARM9 processor is selected. When low, the BB25IC chip boundary scan mode is selected.
The value on this signal is latched when NPOR de-asserts (goes high). When NPOR is de
asserted (high) and the JTAG emulation mode has been latched, this signal provides the
return clock to the ARM Multi-ICE. Because the ARM9 functions off a single clock domain,
the TCK has to be internally synchronised in the ARM9. This can cause a variable length delay
in the validity of the TDO signal. The RTCK is a synchronised version of the TCK signal. The
Multi-ICE uses the RTCK output signal to indicate when the TDO signal is valid. The signal
return path is DIG_GND. Pull it to VCC (DIG_3V3) through a 1K resistor for normal operation.
NTRST
Type: Test
Direction: Input
Pin: 15
The Test Reset signal. This is the active low JTAG test reset signal. The signal return path is
DIG_GND. Pull it to ground through a 1K resistor for normal operation.
4. SIGNAL DESCRIPTION continued
