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CHAPTER 4 CLOCK GENERATOR
User’s Manual U12697EJ3V0UM
4.4.3 Frequency divider
The frequency divider divides the main system clock oscillator output (f
XX
) and generates various clocks.
4.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,
connect the XT1 and XT2 pins as follows.
XT1 : Connect to V
SS1
XT2 : Leave open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To minimize leakage current, set 1 bit 7 (SBK) of the standby control register
(STBC). In this case also, connect the XT1 and XT2 pins as described above.
