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CHAPTER 4 CLOCK GENERATOR
User’s Manual U12697EJ3V0UM
Figure 4-9. Main System Clock Stop Function (2/2)
(c) Operation when CK2 is set after setting MCK during main system clock operation
MCK
CK2
CST
Main system clock
oscillation
Subsystem clock
oscillation
CPU clock
4.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 6 (CK2) of the standby control register (STBC) set to 1), the
following operations are carried out.
(a) The instruction execution time remains constant ((minimum instruction execution time (61
µ
s when operated
at 32.768 kHz)) irrespective of setting bits 4 and 5 (CK0 and CK1) of the STBC.
(b) Watchdog timer continues operating.
Caution Do not set the STOP mode while the subsystem clock is operating.
4.6 Changing System Clock and CPU Clock Settings
The system clock and CPU clock can be switched by means of bits 4 to 6 (CK0 to CK2) of the standby control
register (STBC).
Whether the system is operating on the main system clock or the subsystem clock can be determined by the value
of bit 0 (CST) of the clock status register (PCS).
