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CHAPTER 4 CLOCK GENERATOR
User’s Manual U12697EJ3V0UM
This section describes the switching procedure between the system clock and the CPU clock.
Figure 4-10. System Clock and CPU Clock Switching
(1) The CPU is reset by setting the RESET signal to low level after power application. After that, when reset is
released by setting the RESET signal to high level, the main system clock starts oscillating. At this time, the
oscillation stabilization time (2
19
/f
X
) is secured automatically.
After that, the CPU starts operation at the minimum speed of the main system clock (1,280 ns: @ 12.5 MHz
operation).
(2) After the lapse of a sufficient time for the V
DD
voltage to increase to enable operation at maximum speed, the
STBC and CC are rewritten and maximum-speed operation is carried out.
(3) Upon detection of a decrease in the V
DD
voltage due to an interrupt, the main system clock is switched to the
subsystem clock (which must be in a stable oscillation state).
(4) Upon detection of V
DD
voltage reset due to an interrupt, 0 is set to STBC bit 2 (MCK) and oscillation of the
main system clock is started. After the lapse of time required for stabilization of oscillation, STBC is rewritten
and maximum-speed operation is resumed.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation time has been secured by the program before switching back to the main
system clock.
V
DD
f
XX
Minimum
speed
operation
Wait (41.9 ms: 12.5 MHz)
Internal reset operation
Maximum speed
operation
Subsystem clock
operation
Highest-speed
operation
f
XX
f
XX
f
XT
RESET
System clock
CPU clock
Interrupt
request
signal
