CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
User’s Manual U12697EJ3V0UM
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(2) Asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2)
ASIS1 and ASIS2 are registers used display the type of error when a receive error occurs.
ASIS1 and ASIS2 can be read by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIS1 and ASIS2 to 00H.
Figure 16-4. Format of the Asynchronous Serial Interface Status Registers 1 and 2 (ASIS1, ASIS2)
Address: 0FF72H, 0FF73H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
ASISn
0
0
0
0
0
PEn
FEn
OVEn
PEn
Parity error flag
0
Parity error not generated
1
Parity error generated
(when parity of transmit data does not match)
FEn
Framing error flag
0
Framing error not generated
1
Framing error generated
Note 1
(when stop bit(s) is not detected)
OVEn
Overrun error flag
0
Overrun error not generated
1
Overrun error generated
Note 2
(When next receive operation is completed before data from receive buffer
register is read)
Notes 1.
Even if the stop bit length has been set to 2 bits with bit 2 (SLn) of asynchronous serial interface
mode register n (ASIMn), stop bit detection during reception is only 1 bit.
2.
Be sure to read receive buffer register n (RXBn) when an overrun error occurs.
An overrun error is generated each time data is received until RXBn is read.
Remark
n = 1, 2
(3) Baud rate generator control registers 1 and 2 (BRGC1, BRGC2)
BRGC1 and BRGC2 are registers used to set the serial clock of the asynchronous serial interface.
BRGC1 and BRGC2 are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets BRGC1 and BRGC2 to 00H.
