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CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
Figure 18-1. Serial Bus Configuration Example in I
2
C Bus Mode
Master CPU 1
Slave CPU 1
SDA0
SCL0
Serial data bus
Serial clock
Slave CPU 2
Address 1
Address 2
Slave IC
Address 3
Slave IC
Address N
+V
DD0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
+V
DD0
Master CPU 2
Slave CPU 3
18.2 Configuration
The clocked serial interface in the I
2
C bus mode includes the following hardware.
Figure 18-2 is a block diagram of clocked serial interface (IIC0) in the I
2
C bus mode.
Table 18-1. I
2
C Bus Mode Configuration
Item
Configuration
Registers
Serial shift register 0 (IIC0)
Slave address register 0 (SVA0)
Control registers
I
2
C bus control register 0 (IICC0)
I
2
C bus status register 0 (IICS0)
Prescaler mode register 0 for the serial clock (SPRM0)
