304
CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
Figure 18-4. Format of I
2
C Bus Status Register 0 (IICS0) (3/3)
ACKD0
Acknowledge detection
0
The acknowledge is not detected.
1
The acknowledge is detected.
Clear condition (ACKD0 = 0)
Set condition (ACKD0 = 1)
•
When the stop condition is detected
When the SDA0 line is low at the rising edge of the
•
At the rising edge of the first clock in the next byte
ninth clock of SCL0
•
Cleared by LREL0 = 1
•
When IICE0 = 1
→
0
•
When RESET is input
STD0
Start condition detection
0
The start condition is not detected.
1
The start condition is detected. This indicates the address transfer period.
Clear condition (STD0 = 0)
Set condition (STD0 = 1)
•
When the stop condition is detected
•
When the start condition is detected
•
At the rising edge of the first clock of the next byte
after transferring the address
•
Cleared by LREL0 = 1
•
When IICE0 = 1
→
0
•
When RESET is input
SPD0
Stop condition detection
0
The stop condition is not detected.
1
The stop condition is detected. Communication is ended by the master, and the bus is released.
Clear condition (SPD0 = 0)
Set condition (SPD0 = 1)
•
After the bit is set, at the rising edge of the first
•
When the stop condition is detected
clock in the address transfer byte after detecting the
start condition
•
When IICE0 = 1
→
0
•
When RESET is input
Remark
LREL0: Bit 6 of I
2
C bus control register 0 (IICC0)
IICE0:
Bit 7 of I
2
C bus control register 0 (IICC0)
