305
CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
(3) Prescaler mode register 0 for the serial clock (SPRM0)
The SPRM0 register sets the transfer clock of the I
2
C bus.
SPRM0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SPRM0 to 00H.
Figure 18-5. Format of Prescaler Mode Register 0 for Serial Clock (SPRM0) (1/2)
Address: 0FFB2H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
3
2
1
0
SPRM0
0
0
CLD
DAD
SMC
DFC
CL1
CL0
CLD
SCL0 line level detection (valid only when IICE0 = 1)
0
Detects a low SCL0 line.
1
Detects a high SCL0 line.
Clear condition (CLD = 0)
Set condition (CLD = 1)
•
When the SCL0 line is low
•
When the SCL0 line is high
•
When IICE0 = 0
•
When RESET is input
DAD
SDA0 line level detection (valid only when IICE0 = 1)
0
Detects a low SDA0 line.
1
Detects a high SDA0 line.
Clear condition (DAD = 0)
Set condition (DAD = 1)
•
When the SDA0 line is low
•
When the SDA0 line is high
•
When IICE0 = 0
•
When RESET is input
Note
Bits 4 and 5 are read only.
