306
CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
Figure 18-5. Format of Prescaler Mode Register 0 for Serial Clock (SPRM0) (2/2)
SMC
Note 1
DFC
Note 2
CL1
CL0
Transfer clock
f
XX
setting allowable range
0
1/0
0
0
f
XX
/44
2 to 4.19 MHz
0
1/0
0
1
f
XX
/86
4.19 to 8.38 MHz
0
1/0
1
0
f
XX
/172
8.38 to 12.5 MHz
0
1/0
1
1
TM2 output/66
1
1/0
0
1/0
f
XX
/24
4 to 8.38 MHz
1
1/0
1
0
f
XX
/48
8 to 12.5 MHz
1
1/0
1
1
TM2 output/18
Notes 1.
SMC: Bit to change operation mode
0: Operates in normal mode
1: Operates in high-speed mode
2.
DFC: Bit to control digital filter operation
0: Digital filter off
1: Digital filter on
Cautions 1. Rewrite the SPRM0 after clearing the IICE0.
2. Set the transfer clock as follows:
When SMC = 0: 100 kHz or below
When SMC = 1: 400 kHz or below
Remarks 1.
IICE0: Bit 7 of I
2
C bus control register 0 (IICC0)
2.
The transfer clock does not change due to the ON/OFF setting of bit 2 (DFC) in high-speed mode.
3.
IIC clock: Clock frequency when f
XX
/N is selected
N
×
T + t
R
+ t
F
N/2
×
T
N/2
×
T
t
R
t
F
SCLn
SCLn inverts
SCLn inverts
SCLn inverts
IIC clock frequency: f
SCL
= 1/(N
×
T + tR + tF)
T = 1/f
XX
, tR: SCLn rise time, tF: SCLn fall time
Example
When f
XX
= 12.5 MHz, N = 172, t
R
= 200 ns, t
F
= 50 ns
IIC clock frequency: 1/(172
×
80 ns + 200 ns + 50 ns)
≅
71.4 kHz
.
.