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CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
18.5.2 Address
The 7-bit data following the start condition defines the address.
The address is 7-bit data that is output so that the master selects a specific slave from the multiple slaves connected
to the bus line. Therefore, the slaves on the bus line must have different addresses.
The slave detects this condition by hardware, and determines whether the 7-bit data matches slave address register
0 (SVA0). After the slave was selected when the 7-bit data matched the SVA0 value, communication with the master
continues until the master sends a start or stop condition.
Figure 18-9. Address
SCL0
SDA0
INTIIC0
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
Address
Note
Note
When the base address or extended code was received during slave operation, INTIIC0 is not generated.
The address is output by matching the slave address and matching the transfer direction described in
18.5.3
Transfer direction specification
to serial shift register 0 (IIC0) in 8 bits. In addition, the received address is written
to IIC0.
The slave address is allocated to the higher seven bits of IIC0.
18.5.3 Transfer direction specification
Since the master specifies the transfer direction after the 7-bit address, 1-bit data is transmitted.
A transfer direction specification bit of 0 indicates that the master transmits the data to the slave.
A transfer direction specification bit of 1 indicates that the master receives the data from the slave.
Figure 18-10. Transfer Direction Specification
Note
When the base address or extended code is received during slave operation, INTIIC0 is not generated.
SCL0
SDA0
INTIIC0
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
Transfer direction
specification
Note
