335
CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
18.5.11 Extended codes
(1) If the most significant four bits of the receiving address are “0000” or “1111”, an extended code is received and
the extended code received flag (EXC0) is set. The interrupt request (INTIIC0) is generated at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
(2) In 10-bit address transfers, the following occurs when “111110XX” is set in SVA0 and “111110XX0” is transferred
from the master. However, INTIIC0 is generated at the falling edge of the eighth clock.
•
Higher 4 bits of data match: EXC0 = 1
Note
•
7-bit data match:
COI0 = 1
Note
Note
EXC0: Bit 5 of I
2
C bus status register 0 (IICS0)
COI0:
Bit 4 of I
2
C bus status register 0 (IICS0)
(3) Since the processing after an interrupt request is generated differs depending on the data that follows the
extended code, this processing is performed by software.
For example, when operation as a slave is not desired after an extended code is received, enter the next
communication wait state by setting bit 6 (LREL0) = 1 of I
2
C bus control register 0 (IICC0).
Table 18-3. Definitions of Extended Code Bits
Slave Address
R/W Bit
Description
0000 000
0
General call address
0000 000
1
Start byte
0000 001
×
CBUS address
0000 010
×
Address reserved in the different bus format
1111 0
××
×
10-bit slave address setting
18.5.12 Arbitration
When multiple masters simultaneously output start conditions (when STT0 = 1 occurs before STD0 = 1
Note
), the
master communicates while the clock is adjusted until the data differ. This operation is called arbitration.
A master that failed arbitration sets the arbitration failed flag (ALD0) of I
2
C bus status register 0 (IICS0) at the timing
of the failed arbitration. The SCL0 and SDA0 lines enter the high impedance state, and the bus is released.
Failed arbitration is detected when ALD0 = 1 by software at the timing of the interrupt request generated next (eighth
or ninth clock, stop condition detection, etc.).
At the timing for generating the interrupt request, refer to
18.5.7 I
2
C interrupt request (INTIIC0)
.
Note
STD0: Bit 1 in I
2
C bus status register 0 (IICS0)
STT0 : Bit 1 in I
2
C bus control register 0 (IICC0)
