338
CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
18.5.14 Communication reservation
When you want the master to communicate after being in the not participating state in the bus, the start condition
can be transmitted when a bus is released by reserving communication. The following two states are included when
the bus does not participate.
•
When there was no arbitration in the master and the slave
•
When the extended code is received and operation is not as a slave (bus released when ACK is not returned,
and bit 6 (LREL0) = 1 in the I
2
C bus control register (IICC0))
When bit 1 (STT0) of IICC0 is set in the not participating state in the bus, after the bus is released (after stop condition
detection), the start condition is automatically generated, and the wait state is entered. When the bus release is
detected (stop condition detection), the address transfer starts as the master by the write operation of serial shift
register 0 (IIC0). In this case, set bit 4 (SPIE0) in IICC0.
When STT0 is set, whether it operates as a start condition or for communication reservation is determined by the
bus state.
•
When the bus is released ··············································· Start condition generation
•
When the bus is not released (standby state) ··············· Communication reservation
The method that detects the operation of STT0 sets STT0 and verifies the STT0 bit again after the wait time elapses.
Use the software to save the wait time which is a time listed in Table 18-5. The wait time can be set by bits 3,
1, and 0 (SMC, CL1, CL0) in prescaler mode register 0 for the serial clock (SPRM0).
Table 18-5. Wait Times
SMC
CL1
CL0
Wait Time
0
0
0
26 clocks
×
1/f
XX
0
0
1
46 clocks
×
1/f
XX
0
1
0
92 clocks
×
1/f
XX
0
1
1
37 clocks
×
1/TM2 output
1
0
0
16 clocks
×
1/f
XX
1
0
1
1
1
0
32 clocks
×
1/f
XX
1
1
1
13 clocks
×
1/TM2 output
