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CHAPTER 19 CLOCK OUTPUT FUNCTION
User’s Manual U12697EJ3V0UM
19.2 Configuration
The clock output function includes the following hardware.
Table 19-1. Configuration of Clock Output Function
Item
Configuration
Control registers
Clock output control register (CKS)
Port 2 mode register (PM2)
Figure 19-2. Block Diagram of Clock Output Function
CLOE CCS3 CCS2 CCS1 CCS0
Internal Bus
Synchronization
circuit
PCL/P23
Clock output control register (CKS)
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
4
f
XX
f
XT
f
XX
/2
f
XX
/2
2
Port 2 mode register (PM2)
PM23
P23 output latch
Selector
19.3 Control Registers
The following two registers are used to control the clock output function.
• Clock output control register (CKS)
• Port 2 mode register (PM2)
(1) Clock output control register (CKS)
This register sets the PCL output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CKS to 00H.
Remark
CKS provides a function for setting the buzzer output clock besides setting the PCL output clock.
