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CHAPTER 22 INTERRUPT FUNCTIONS
User’s Manual U12697EJ3V0UM
22.6 Non-Maskable Interrupt Acknowledgment Operation
Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be
acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or
a non-maskable interrupt of higher priority.
The relative priorities of non-maskable interrupts are set by the WDT4 bit of the watchdog timer mode register
(WDM) (see
22.3.5 Watchdog timer mode register (WDM)
).
Except in the cases described in
22.9 When Interrupt Requests and Macro Service Are Temporarily Held
Pending
, a non-maskable interrupt request is acknowledged immediately. When a non-maskable interrupt request
is acknowledged, the program status word (PSW) and program counter (PC) are saved in that order to the stack,
the IE flag is cleared (0), the in-service priority register (ISPR) bit corresponding to the acknowledged non-maskable
interrupt is set (1), the vector table contents are loaded into the PC, and a branch is performed. The ISPR bit that
is set (1) is the NMIS bit in the case of a non-maskable interrupt due to edge input to the NMI pin, and the WDTS
bit in the case of watchdog timer overflow.
When the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same
priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than
the non-maskable interrupt currently being executed are held pending. A pending non-maskable interrupt is
acknowledge after completion of the non-maskable interrupt service program currently being executed (after
execution of the RETI instruction). However, even if the same non-maskable interrupt request is generated more
than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is
acknowledged after completion of the non-maskable interrupt service program.
