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CHAPTER 22 INTERRUPT FUNCTIONS
User’s Manual U12697EJ3V0UM
Figure 22-14. Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Service (3/3)
Notes 1.
Low default priority
2.
High default priority
Remarks 1.
“a” to “z” in the figure above are arbitrary names used to differentiate between the interrupt requests
and macro service requests.
2.
High/low default priorities in the figure indicate the relative priority levels of the two interrupt
requests.
Main routine
EI
EI
EI
EI
EI
EI
Interrupt request q
(Level 3)
Interrupt
request s
(Level 1)
Interrupt request u
(Level 0)
Interrupt
request v
(Level 0)
w macro service
q servicing
r servicing
s servicing
t servicing
u servicing
v servicing
x servicing
y servicing
z servicing
Interrupt request x
(Level 1)
Interrupt
request r
(Level 2)
Interrupt
request t
(Level 0)
Interrupt
request y
Note 1
(Level 2)
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC register is set (1),
only macro service requests and non-
maskable interrupts generate nesting
beyond this.
If the PRSL bit of the IMC register is
cleared (0), level 3 interrupts can also be
nested during level 3 interrupt servicing
(see
Figure 22-16
).
Even though the interrupt enabled state is
set during servicing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
serviced irrespective of its level and even
though there is a peding interrupt with a
higher priority level.
Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.
Interrupt
request z
Note 2
(Level 2)
Macro
service
request w
(Level 3)
