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NEC mPD784225 Series, User Manual


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CHAPTER 22  INTERRUPT FUNCTIONS

424

User’s Manual  U12697EJ3V0UM

Figure 22-34.  Single-Phase Excitation of 4-Phase Stepper Motor

Phase A

Phase B

Phase C

 Phase D

1 cycle
(4 patterns)

1

2

3

4

1

2

3

Figure 22-35.  1-2-Phase Excitation of 4-Phase Stepper Motor

Phase A

Phase B

Phase C

Phase D

1 cycle
(8 patterns)

1

2

3

4

5

6

7

8

1

2

3

4

8

5

Summary of Contents for mPD784225 Series

Page 1: ...8 Bit Single Chip Microcontrollers Hardware PD784224 PD784224Y PD784225 PD784225Y PD78F4225 PD78F4225Y Document No U12697EJ3V0UM00 3rd edition Date Published April 2001 N CP K 1997 2000 User s Manual...

Page 2: ...2 User s Manual U12697EJ3V0UM MEMO...

Page 3: ...g or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched wi...

Page 4: ...tandard Specification as defined by Philips The application circuits and their parameters are for reference only and are not intended for use in actual design ins The export of these products from Jap...

Page 5: ...nnot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety...

Page 6: ...Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Ita...

Page 7: ...ure 18 17 Communication Reservation Procedure CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS p 450 Modification of Figure 23 8 Read Modify Write Timing for External Memory in External Memory Expansion Mode...

Page 8: ...duct Be sure to read the cautions in the text of each chapter and summarized at the end of each chapter How to Read This Manual It is assumed that the readers of this manual have general knowledge abo...

Page 9: ...the PD784225 Subseries and the PD784225Y Subseries The only functional difference between the PD784225 Subseries and PD784225Y Subseries is the clocked serial interface The two subseries share all ot...

Page 10: ...ne l letter l I capital i When writing B 7 1 6 0 4 A 3 2 1 0 EDC 1 0 5 Read the value that conforms to the operating state When reading Write 0 or 1 The operation is not affected by either value Must...

Page 11: ...it Emulator U12903E IE 784225 NS EM1 Emulation Board U13742E SM78K4 System Simulator Windows Based Reference U10093E ID78K4 NS Integrated Debugger Windows Based Reference U12796E ID78K4 Integrated Deb...

Page 12: ...3 3 Base Area 62 3 3 1 Vector table area 63 3 3 2 CALLT instruction table area 64 3 3 3 CALLF instruction entry area 64 3 4 Internal Data Area 65 3 4 1 Internal RAM area 66 3 4 2 Special function regi...

Page 13: ...5 2 6 Port 5 122 5 2 7 Port 6 124 5 2 8 Port 7 128 5 2 9 Port 12 131 5 2 10 Port 13 132 5 3 Control Registers 133 5 4 Operations 138 5 4 1 Writing to I O port 138 5 4 2 Reading from I O port 138 5 4...

Page 14: ...onfiguration 205 10 3 Control Registers 208 10 4 Operation 212 10 4 1 Operation as interval timer 8 bit operation 212 10 4 2 Operation as interval timer 16 bit operation 217 10 5 Cautions 218 CHAPTER...

Page 15: ...ode 261 16 2 1 Configuration 261 16 2 2 Control registers 264 16 3 Operation 268 16 3 1 Operation stop mode 268 16 3 2 Asynchronous serial interface UART mode 269 16 3 3 Standby mode operation 280 16...

Page 16: ...ON 358 21 1 Control Registers 358 21 2 Edge Detection of P00 to P05 Pins 359 CHAPTER 22 INTERRUPT FUNCTIONS 360 22 1 Interrupt Request Sources 361 22 1 1 Software interrupts 363 22 1 2 Operand error i...

Page 17: ...2 10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service 432 22 11 Interrupt and Macro Service Operation Timing 432 22 11 1 Interrupt acknowledge processing time 433...

Page 18: ...ation 510 26 3 Control Register for ROM Correction 512 26 4 Usage of ROM Correction 514 26 5 Conditions for Executing ROM Correction 515 CHAPTER 27 PD78F4225 AND PD78F4225Y PROGRAMMING 516 27 1 Intern...

Page 19: ...19 User s Manual U12697EJ3V0UM APPENDIX C EMBEDDED SOFTWARE 568 APPENDIX D REGISTER INDEX 570 D 1 Register Index 570 D 2 Register Index Alphabetical Order 573 APPENDIX E REVISION HISTORY 577...

Page 20: ...9 4 6 External Circuit of Main System Clock Oscillator 100 4 7 External Circuit of Subsystem Clock Oscillator 101 4 8 Incorrent Examples of Resonator Connection 102 4 9 Main System Clock Stop Function...

Page 21: ...or Pulse Width Measurement with Free Running Counter 164 8 12 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified 164 8 13 Control Register Settings for Measurement o...

Page 22: ...3 10 1 Block Diagram of 8 Bit Timers 5 and 6 205 10 2 Format of 8 Bit Timer Mode Control Register 5 TMC5 208 10 3 Format of 8 Bit Timer Mode Control Register 6 TMC6 209 10 4 Format of Prescaler Mode R...

Page 23: ...Wire Serial I O Mode 260 16 2 Block Diagram in Asynchronous Serial Interface Mode 262 16 3 Format of Asynchronous Serial Interface Mode Registers 1 and 2 ASIM1 ASIM2 265 16 4 Format of the Asynchronou...

Page 24: ...343 18 20 Master Slave Communication Example When Master and Slave Select 9 Clock Waits 345 18 21 Slave Master Communication Example When Master and Slave Select 9 Clock Waits 348 19 1 Remote Control...

Page 25: ...Transfer Processing Flow Type A 406 22 24 Type A Macro Service Channel 408 22 25 Asynchronous Serial Reception 409 22 26 Macro Service Data Transfer Processing Flow Type B 411 22 27 Type B Macro Servi...

Page 26: ...Register PCS 469 24 4 Format of Oscillation Stabilization Time Specification Register OSTS 471 24 5 Operations After Releasing HALT Mode 476 24 6 Operations After Releasing STOP Mode 485 24 7 Releasi...

Page 27: ...ng UART1 522 B 1 Development Tool Configuration 557 B 2 Package Drawing of EV 9200GC 80 Reference Unit mm 565 B 3 Recommended Board Installation Pattern of EV 9200GC 80 Reference Unit mm 566 B 4 TGK 0...

Page 28: ...ut Port 143 7 1 Timer Operation 146 8 1 Configuration of 16 Bit Timer Event Counter 150 8 2 Valid Edge of TI00 Pin and Capture Trigger of CR00 152 8 3 Valid Edge of TI01 Pin and Capture Trigger of CR0...

Page 29: ...ssing Time 433 22 8 Macro Service Processing Time 434 23 1 Pin Functions in External Memory Expansion Mode 438 23 2 Pin States in Ports 4 to 6 in External Memory Expansion Mode 438 23 3 Settings of Pr...

Page 30: ...mmunication Modes 519 27 4 Major Functions of On Board Overwrite Mode 520 28 1 8 Bit Addressing Instructions 551 28 2 16 Bit Addressing Instructions 552 28 3 24 Bit Addressing Instructions 553 28 4 Bi...

Page 31: ...high performance timer counter an 8 bit A D converter an 8 bit D A converter and an independent 2 channel serial interface The PD784224 is the PD784225 with a 96 KB mask ROM and a 3 584 byte RAM The P...

Page 32: ...hip 10 bit A D converter For DC inverter control On chip IEBusTM controller Software servo control On chip analog circuit for VCRs Enhanced timer Supports multimaster I2 C bus Enhanced functions of th...

Page 33: ...resistors 57 inputs LED direct drive possible 16 outputs Timers 16 bit timer event counter 1 unit 8 bit timer event counter 2 units 8 bit timer 2 units Watch timer 1 channel Watchdog timer 1 channel...

Page 34: ...QFP 14 14 Flash memory PD78F4225GK 9EU 80 pin plastic TQFP fine pitch 12 12 Flash memory Note Under development Remark indicates ROM code suffix 2 PD784225Y Subseries Part Number Package Internal ROM...

Page 35: ...ote 1 P26 SO0 P27 SCK0 SCL0Note 1 P40 AD0 P41 AD1 RESET P127 RTP7 P126 RTP6 P125 RTP5 P124 RTP4 P123 RTP3 P122 RPT2 P121 RTP1 P120 RTP0 P37 EXA P36 TI01 P35 TI00 P34 TI2 P33 TI1 P32 TO2 P31 TO1 P30 TO...

Page 36: ...PP pin via a pull down resistor For the pull down connection use of a resistor with a resistance between 470 and 10 k is recommended 3 Connect the AVDD pin to VDD0 4 Connect the AVSS pin to VSS0 Remar...

Page 37: ...to SI2 Serial input EXA External access status output SO0 to SO2 Serial output INTP0 to INTP5 Interrupt from peripherals TEST Test NMI Non maskable interrupt TI00 TI01 TI1 TI2 Timer input P00 to P05 P...

Page 38: ...e generator Baud rate generator RxD1 SI1 TxD1 SO1 ASCK1 SCK1 RxD2 SI2 TxD2 SO2 ASCK2 SCK2 SI0 SDA0Note 1 SO0 SCK0 SCL0Note 1 Bus I F UART IOE1 RD ASTB WR WAIT AD0 to AD7 A8 to A15 A16 to A19 Port 1 P1...

Page 39: ...e 1 MB of combined program and data space I O ports Total 67 CMOS input 8 CMOS I O 59 Pins with added Pins with pull up 57 functionsNote resistors LED direct drive outputs 16 Real time output ports 4...

Page 40: ...output Select from fXX 210 fXX 211 fXX 212 fXX 213 Watch timer 1 channel Watchdog timer 1 channel Standby HALT STOP IDLE modes In the low power consumption mode CPU operation by subsystem clock HALT I...

Page 41: ...t One shot pulse output Pulse width measurement 2 inputs Number of interrupt requests 2 1 1 1 1 Note Can also be used as 16 bit timer event counter or 16 bit timer when connected in cascade When using...

Page 42: ...78F4225Y Internal ROM 96 KB 128 KB 128 KB mask ROM mask ROM flash memory Internal RAM 3 584 bytes 4 352 bytes Power supply voltage VDD 1 8 to 5 5 V VDD 1 9 to 5 5 V Internal memory size switching regi...

Page 43: ...pull up resistor can be specified by software in 1 bit units Port 1 P1 8 bit input only port Port 2 P2 8 bit I O port Input output can be specified in 1 bit units Regardless of whether the input or o...

Page 44: ...be driven directly Port 6 P6 8 bit I O port Input output can be specified in 1 bit units For input mode pins use of on chip pull up resistors can be specified for all pins by software Port 7 P7 3 bit...

Page 45: ...ASCK1 Input P22 SCK1 Baud rate clock input UART1 ASCK2 P72 SCK2 Baud rate clock input UART2 SI0 Input P25 SDA0Note Serial data input 3 wire serial I O0 SI1 P20 RxD1 Serial data input 3 wire serial I...

Page 46: ...Input System reset input X1 Crystal connection for main system clock oscillation X2 XT1 Input Crystal connection for subsystem clock oscillation XT2 ANI0 to ANI7 Input P10 to P17 Analog voltage input...

Page 47: ...ing pull up resistor option register 0 b Control mode These pins function as external interrupt request inputs i INTP0 to INTP5 INTP0 to INTP5 are external interrupt request input pins for which the v...

Page 48: ...des can be specified in 1 bit units a Port mode These pins function as an 8 bit I O port Input or output can be specified in 1 bit units by means of the port 2 mode register Regardless of whether the...

Page 49: ...the 16 bit timer event counter This is also used as the capture trigger signal input pin to capture compare registers 00 and 01 ii TI01 This is the capture trigger signal input pin to capture compare...

Page 50: ...can be specified in 1 bit units by means of the port 6 mode register When used as an input port pull up resistors can be connected in 8 bit units with bit 6 PUO6 of the pull up resistor option registe...

Page 51: ...Control mode These pins function as a real time output port RTP0 to RTP7 that outputs data synchronized with a trigger When the pins specified as the real time output port are read 0 is read 10 P130...

Page 52: ...nator connection pins for subsystem clock oscillation When an external clock is supplied input this clock signal at XT1 and its inverted signal at XT2 17 VDD0 VDD1 VDD0 is the positive power supply pi...

Page 53: ...put Independently connect to VSS0 via a resistor P01 INTP1 Output Leave open P02 INTP2 NMI P03 INTP3 to P05 INTP5 P10 ANI0 to P17 ANI7 9 Input Connect to VSS0 or VDD0 P20 RxD1 SI1 10 I I O Input Indep...

Page 54: ...P131 ANO1 12 D Output Leave open RESET 2 G Input XT1 16 Connect to VSS0 XT2 Leave open AVREF1 Connect to VDD0 AVDD AVSS Connect to VSS0 TEST VPP Note Connect directly to VSS0 or pull down For the pul...

Page 55: ...Data Output disable Input enable VDD0 P ch VDD0 P ch IN OUT N ch VSS0 Data Output disable P ch IN OUT VDD0 N ch Input enable P ch VDD0 Pull up enable VSS0 Data Output disable P ch IN OUT VDD0 N ch P c...

Page 56: ...le Data VDD0 Open drain VSS0 Output disable N ch P ch P ch IN OUT VDD0 Pull up enable Data VDD0 Open drain VSS0 N ch P ch VDD0 Data Output disable Input enable Analog output voltage IN OUT P ch N ch V...

Page 57: ...ea differs depending on LOCATION instruction special function registers and internal RAM The LOCATION instruction must always be executed after releasing reset and cannot be used more than once The pr...

Page 58: ...data area in the on chip ROM cannot be used while the LOCATION 0H instruction is executed Part Number Unused Area PD784224 0F100H to 0FFFFH 3 840 bytes PD784225 0EE00H to 0FFFFH 4 608 bytes External...

Page 59: ...KB Program data area Note 3 CALLT table area 64 bytes Vector table area 64 bytes Internal RAM 3 584 bytes External memory Note 1 980 736 bytes 256 bytes Internal ROM 96 KB On execution of LOCATION 0H...

Page 60: ...KB Program data area Note 3 CALLT table area 64 bytes Vector table area 64 bytes Internal RAM 4 352 bytes External memory Note 1 912 896 bytes 256 bytes Internal ROM 128 KB On execution of LOCATION 0H...

Page 61: ...000H to 1FFFFH The internal ROM can be accessed at high speed Usually a fetch is at the same speed as an external ROM fetch By setting the IFCH bit of the memory expansion mode register MM to 1 the hi...

Page 62: ...essing mode instruction address addressing 16 bit register indirect addressing mode Short direct 16 bit memory indirect addressing mode This base area is allocated in the vector table area CALLT instr...

Page 63: ...y or data memory The values written in the vector table are 16 bit values Therefore branching can only be to the base area Table 3 1 Vector Table Address Interrupt Source Vector Table Address Interrup...

Page 64: ...nstruction table the area can be used as normal program memory or data memory 3 3 3 CALLF instruction entry area The area from 00800H to 00FFFH can be for direct subroutine calls in the 2 byte call in...

Page 65: ...n updating is not possible The program following a reset clear must be as shown in the example If the internal data area and another area are allocated to the same address the internal data area becom...

Page 66: ...rnal RAM Area List Internal RAM Internal RAM Area Product Name Peripheral RAM PRAM Internal High Speed RAM IRAM PD784224 3 584 bytes 3 072 bytes 512 bytes 0F100H to 0FEFFH 0F100H to 0FCFFH 0FD00H to 0...

Page 67: ...the productNote General purpose register area Macro service control word area Available range for short direct addressing 1 Available range for short direct addressing 2 Internal high speed RAM Perip...

Page 68: ...address that is mapped by IRAM the CPU inadvertently loops The following areas are reserved in IRAM General purpose register area FE80H to FEFFH Macro service control word area FE06H to FE39H Macro s...

Page 69: ...0H is added to the values in the text 3 4 3 External SFR area In the products of the PD784225 Subseries the 16 byte area of the 0FFD0H to 0FFDFH area during LOCATION 0H instruction execution or 0FFFD0...

Page 70: ...struction RESET input sets IMS to FFH Figure 3 4 Format of Internal Memory Size Switching Register IMS Address 0FFFCH After reset FFH W Symbol 7 6 5 4 3 2 1 0 IMS 1 1 ROM1 ROM0 1 1 RAM1 RAM0 ROM1 ROM0...

Page 71: ...Counter PC 19 0 PC 3 7 2 Program status word PSW The program status word PSW is a 16 bit register that consists of various flags that are set and reset based on the result of the instruction executio...

Page 72: ...ested by a conditional branch instruction Parity flag action The results of executing the logical instructions shift rotate instructions and CHKL and CHKLA instructions are set to 1 when an even numbe...

Page 73: ...1 21 P V 0 CY 3 Interrupt request enable flag IE This flag controls the CPU interrupt request acceptance If IE is 0 interrupts are disabled and only non maskable interrupts and unmasked macro services...

Page 74: ...indicates that the MSB in the operation result is 1 The flag is set to 1 when the MSB of the operation result is 1 If 0 the flag is reset to 0 The S flag state can be tested by the conditional branch...

Page 75: ...ries programs will be used By setting the RSS bit to 0 in all programs writing and debugging programs become more efficient Even if a program where the RSS bit is set to 1 is used when possible it is...

Page 76: ...SWL 5 MOV B A This description corresponds to MOV R3 R1 When RSS 1 RSS 1 RSS quasi directive SET1 PSWL 5 MOV B A This description corresponds to MOV R7 R5 2 Generation of instruction code in the RA78K...

Page 77: ...and C registers that are used in indexed addressing and based indexed addressing cannot be described as R1 R3 R2 or R5 R7 R6 3 Usage warnings Switching the RSS bit obtains the same effect as holding t...

Page 78: ...ero The contents of the SP are decremented before writing to the stack area and incremented after reading from the stack refer to Figures 3 8 and 3 9 SP is accessed by special instructions Since the S...

Page 79: ...ck SP SP 1 SP 2 SP SP 2 SP SP 1 SP 2 SP 3 SP SP 3 Higher byte Middle byte Lower byte PSWH7 to PSWH4 PSWH7 to PSWH4 PSWL Undefined CALL CALLF CALLT instructions Stack Vectored interrupt Stack SP SP 1 S...

Page 80: ...on Stack SP 1 SP SP SP 2 SP 2 SP 1 SP SP SP 3 Higher byte Middle byte Lower byte PSWH7 to PSWH4 PSWH7 to PSWH4 PSWL Note RET instruction Stack RETI RETB instructions Stack SP 2 SP 1 SP SP SP 3 SP 3 SP...

Page 81: ...n addition even when SP is in the undefined state non maskable interrupts can be acknowledged Therefore when the SP is in the undefined state immediately after the reset is cleared and a request for a...

Page 82: ...except for the V U T and W registers for address expansion are mapped to the internal RAM These register sets provide eight banks and can be switched by the software or context switching RESET input...

Page 83: ...t to 1 However use this function only when using a 78K III Series program Remark When changing the register bank and when returning to the original register bank is necessary execute the SEL RBn instr...

Page 84: ...s efficient programs can be written by suitably using the register banks in normal processing or interrupt servicing Each register has the unique functions shown below A R1 This register is primarily...

Page 85: ...except bits 0 to 3 in PSWH VVP RG4 This register functions as a pointer and specifies the base address in register indirect addressing based addressing and based indirect addressing UUP RG5 This regi...

Page 86: ...ch register can be described by its absolute name R0 to R15 RP0 to RP7 RG4 to RG7 For the correspondence refer to Table 3 5 Table 3 5 Correspondence Between Function Names and Absolute Names a 8 bit r...

Page 87: ...ly by reset input Table 3 6 shows the list of special function registers SFRs The meanings of the items are described next Symbol This symbol indicates the on chip SFR In NEC assembler RA78K4 this is...

Page 88: ...timer mode control register 0 TMC0 0FF1AH 16 bit timer output control register 0 TOC0 0FF1CH Prescaler mode register 0 PRM0 0FF20H Port 0 mode register PM0 FFH 0FF22H Port 2 mode register PM2 0FF23H P...

Page 89: ...R W 0FF65H Compare register 60 8 bit timer 6 CR60 0FF68H 8 bit timer mode control register 5 TMC5 TMC5W 0FF69H 8 bit timer mode control register 6 TMC6 0FF6CH Prescaler mode register 5 PRM5 PRM5W 0FF...

Page 90: ...ut buffer register L RTBL 0FF99H Real time output buffer register H RTBH 0FF9AH Real time output port mode register RTPM 0FF9BH Real time output port control register RTPC 0FF9CH Watch timer mode cont...

Page 91: ...rrupt control register INTP5 PIC5 0FFE8H Interrupt control register INTIIC0Note 2 INTCSI0 CSIIC0 0FFE9H Interrupt control register INTSER1 SERIC1 0FFEAH Interrupt control register INTSR1 INTCSI1 SRIC1...

Page 92: ...ted They are FFF00H to FFFFFH when the LOCATION 0FH instruction is executed 3 Stack pointer SP operation Although the entire 1 MB space can be accessed by stack addressing the stack cannot be guarante...

Page 93: ...ng to the subsystem clock 2 Subsystem clock oscillator This circuit oscillates at the frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the...

Page 94: ...in system clock oscillator Subsystem clock oscillator fXT Watch timer clock output function Clock to peripheral hardware CPU clock fCPU Internal system clock fCLK Divider IDLE controller Prescaler Pre...

Page 95: ...dress saved in the stack area indicates the address of the instruction that caused an error Therefore the address that caused an error can be determined from the return address that is saved in the st...

Page 96: ...ically cleared upon cancellation of IDLE mode Cautions 1 When using the STOP mode during external clock input make sure to set to 1 the EXTC bit of the oscillation stabilization time specification reg...

Page 97: ...lator with the same frequency as the external clock or clock output that is half of the original frequency is used to operate the internal circuit CC is set by a 1 bit or 8 bit memory manipulation ins...

Page 98: ...Internal feedback resistor is used 1 Internal feedback resistor is not used CK2 CK1 CK0 CPU clock operating frequency 0 0 0 fXX 0 0 1 fXX 2 0 1 0 fXX 4 0 1 1 fXX 8 1 1 1 fXT Recommendation 1 fXT MCK...

Page 99: ...on stabilization time 0 0 0 0 219 fXX 41 9 ms 0 0 0 1 218 fXX 21 0 ms 0 0 1 0 217 fXX 10 5 ms 0 0 1 1 216 fXX 5 2 ms 0 1 0 0 215 fXX 2 6 ms 0 1 0 1 214 fXX 1 3 ms 0 1 1 0 213 fXX 655 s 0 1 1 1 212 fXX...

Page 100: ...the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin Figure 4 6 shows an exte...

Page 101: ...r wire as follows in the area enclosed by the broken lines in Figures 4 6 and 4 7 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring...

Page 102: ...f Resonator Connection 1 2 a Wiring of connection b Signal lines intersect circuits is too long each other Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Further i...

Page 103: ...nd C fluctuate e Signals are fetched Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 When XT2 and X1 are...

Page 104: ...o use subsystem clocks for low power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VSS1 XT2 Leave open In this state however some current may leak...

Page 105: ...able To decrease current consumption in the STOP mode the subsystem clock feedback resistor can be disconnected to stop the subsystem clock with bit 7 SBK of STBC when the system does not use a subsys...

Page 106: ...n operated with the main system clock the main system clock oscillation does not stop When bit 6 CK2 of the STBC is set to 1 and the operation is switched to subsystem clock operation CST 1 after that...

Page 107: ...e carried out a The instruction execution time remains constant minimum instruction execution time 61 s when operated at 32 768 kHz irrespective of setting bits 4 and 5 CK0 and CK1 of the STBC b Watch...

Page 108: ...re rewritten and maximum speed operation is carried out 3 Upon detection of a decrease in the VDD voltage due to an interrupt the main system clock is switched to the subsystem clock which must be in...

Page 109: ...provided The function of each port is described in Table 5 1 On chip pull up resistors can be specified for ports 0 2 to 7 and 12 by software during input Figure 5 1 Port Configuration Port 7 Port 0...

Page 110: ...able in 1 bit units Port 4 P40 to P47 Input or output can be specified in 1 bit units Specifiable individually for each port Can drive LED directly Port 5 P50 to P57 Input or output can be specified i...

Page 111: ...l up resistor option register 0 regardless of whether the input mode or output mode is specified Port 0 also supports external interrupt request input as an alternate function RESET input sets port 0...

Page 112: ...f P00 to P05 PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P ch WRPM WRPORT RD WRPU VDD Selector Alternate function PU00 to PU05 Output latch P...

Page 113: ...Block Diagram of P10 to P17 RD Internal bus P10 ANI0 to P17 ANI7 Alternate function RD Port 1 read signal Caution Do not execute a read instruction for port 1 when it is used as an analog input port i...

Page 114: ...fied as N ch open drain with a port function control register only the PD784225Y Subseries Port 2 supports serial interface data input output clock input output clock output and buzzer output as alter...

Page 115: ...to P24 and P26 P ch WRPM WRPORT RD WRPU VDD Selector PU21 PU23 PU24 PU26 Output Latch P21 P23 P24 P26 PM21 PM23 PM24 PM26 Internal bus Alternate function P21 SO1 TXD1 P23 PCL P24 BUZ P26 SO0 PU Pull u...

Page 116: ...PF RD WRPU VDD VDD Selector PU25 PF25 PM25 Internal bus P25 SI0 SDA0Note WRPORT Output latch P25 Alternate function Note The SDA0 pin applies only to the PD784225Y Subseries PU Pull up resistor option...

Page 117: ...VDD VDD Selector PU27 PF27 PM27 Internal bus Alternate function P27 SCK0 SCL0Note WRPORT Output latch P27 Alternate function Note The SCL0 pin applies only to the PD784225Y Subseries PU Pull up resis...

Page 118: ...the input mode or output mode is specified Port 3 supports timer input output as an alternate function RESET input sets port 3 to the input mode Figures 5 8 and 5 9 show a block diagram of port 3 Fig...

Page 119: ...agram of P33 to P36 P ch WRPM WRPORT RD WRPU VDD Selector Alternate function PU33 to PU36 Output latch P33 to P36 PM33 to PM36 Internal bus P33 TI1 P34 TI2 P35 TI00 P36 TI01 PU Pull up resistor option...

Page 120: ...rt 4 mode register When the P40 to P47 pins are used as input ports a pull up resistor can be connected in 8 bit units with bit 4 PUO4 of the pull up resistor option register Port 4 can drive LEDs dir...

Page 121: ...to P47 WRPU PUO4 WRPU PM40 to P47 Output latch P40 to P47 WRPU WRPU RDP4 Internal data bus WRPU P40 AD0 to P47 AD7 VDD MM0 to MM3 External access data Internal address bus I O controller PUO Pull up r...

Page 122: ...port 5 mode register When the P50 to P57 pins are used as input ports a pull up resistor can be connected in 8 bit units with bit 5 PUO5 of the pull up resistor option register Port 5 can drive LEDs...

Page 123: ...MM3 WRPM5 PM50 to PM75 RDPU0 WRP5 RDP5 Output latch P50 to P57 RDPM5 VDD0 P50 A8 to P57 A15 Internal data bus Internal address bus I O controller PUO Pull up resistor option register PM Port mode reg...

Page 124: ...rt 6 mode register When pins P60 to P67 are used as input ports a pull up resistor can be connected in 8 bit units with bit 6 PUO6 of the pull up resistor option register Port 6 supports the address b...

Page 125: ...tor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal MM0 to MM3 Bits 0 to 3 of the memory expansion mode register MM WRPU0 PUO6 WRPM6 PM60 to PM63 RDPU0 WRP6 RDP6 Out...

Page 126: ...P67 WRPU0 RDPU0 WRPM6 WRP6 RDP6 RDPM6 PUO6 VDD Internal bus Output latch P64 P65 P67 Selector PM64 PM65 PM67 P64 RD P65 WR P67 ASTB External expansion mode Timing signal for external expansion PUO Pu...

Page 127: ...of P66 PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal WRPU0 RDPU0 WRPM6 WRP6 RDP6 RDPM6 PUO6 VDD P66 WAIT Internal bus Pull up resistor option...

Page 128: ...whether the input mode or output mode is specified Port 7 supports serial interface data input output and clock input output as alternate functions RESET input sets port 7 to the input mode Figures 5...

Page 129: ...3V0UM Figure 5 16 Block Diagram of P71 PU Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal P ch WRPM WRPORT RD WRPU VDD Selector PU71 Output latch P7...

Page 130: ...V0UM Figure 5 17 Block Diagram of P72 P ch WRPM WRPORT RD WRPU VDD Selector Alternate function PU72 Output latch P72 PM72 Internal bus P72 SCK2 ASCK2 PU Pull up resistor option register PM Port mode r...

Page 131: ...the input mode or output mode is specified Port 12 supports the real time output function as an alternate function RESET input sets port 12 to the input mode Figure 5 18 shows a block diagram of port...

Page 132: ...k diagram of port 13 Caution When only either one of the D A converter channels is used with AVREF1 VDD the other pins that are not used as analog outputs must be set as follows Set the port mode regi...

Page 133: ...s are used to set port input output in 1 bit units PM0 PM2 to PM7 PM12 and PM13 are set with a 1 bit or 8 bit memory manipulation instruction respectively RESET input sets port mode registers to FFH W...

Page 134: ...e 3 I O 0 0 SCK2 Input 1 P26 SO0 Output 0 0 Output 0 0 P27 SCK0 Input 1 P120 to P127 RTP0 to RTP7 Output 0 0 Output 0 0 P130 P131Note 1 ANO0 ANO1 Output 1 SCL0Note 3 I O 0 0 P30 to P32 TO0 to TO2 Outp...

Page 135: ...22 PM21 PM20 PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM7 1 1 1 1...

Page 136: ...H 0FF33H 0FF37H 0FF3CH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU0 0 0 PU05 PU04 PU03 PU02 PU01 PU00 PU2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU3 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 PU7 0 0...

Page 137: ...input sets PF2 to 00H Caution Only the PD784225Y Subseries incorporates PF2 When using the I2C bus mode serial interface make sure to specify N ch open drain for the P25 and P27 pins Figure 5 22 Form...

Page 138: ...t pins the output latch contents for pins specified as input are undefined except for the manipulated bit 5 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer ins...

Page 139: ...called the real time output port Since jitter free signals can be output by using the real time output port the operation is optimized for the control of stepping motors for example The port mode or r...

Page 140: ...rol register RTPC Output trigger controller Real time output port mode register RTPM INTP2 INTTM1 INTTM2 Higher 4 bits of real time output buffer register RTBH Lower 4 bits of real time output buffer...

Page 141: ...ses of either RTBL and RTBH are specified the data in both can be read in a batch Table 6 2 lists the operations for manipulating RTBL and RTBH Figure 6 2 Configuration of Real Time Output Buffer Regi...

Page 142: ...real time output port mode and port mode selections in 1 bit units RTPM is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets RTPM to 00H Figure 6 3 Format of Real Time Output Po...

Page 143: ...1 Operation enabledNote BYTE Real time output port operation mode 0 4 bits 2 channels 1 8 bits 1 channel EXTR Real time output control by INTP2 0 Do not set INTP2 as real time output trigger 1 Set INT...

Page 144: ...ut port are output from bits RTP0 to RTP7 A port set in the port mode by RTPM can be used as a general purpose I O port When the real time output operation is disabled by RTPOE 0 RTP0 to RTP7 output z...

Page 145: ...eal time output buffer registers RTBH RTBL 3 Enable real time output operation RTPOE 1 4 After generating the selected transfer trigger the RTBH and RTBL values are output from the pin Set the next re...

Page 146: ...tion as six units of timer event counters Table 7 1 Timer Operation Name 16 Bit Timer 8 Bit Timer 8 Bit Timer 8 Bit Timer 5 8 Bit Timer 6 Item Event Counter Event Counter 1 Event Counter 2 Count width...

Page 147: ...ear INTTM00 INTTM01 TO0 Selector Selector Output controller 8 bit timer event counter 1 fXX 29 fXX 27 fXX 25 fXX 24 fXX 23 fXX 22 TI1 8 bit timer counter 1 TM1 8 bit compare register 10 CR10 8 Clear O...

Page 148: ...8 bit timer 5 fXX 29 fXX 27 fXX 25 fXX 24 fXX 23 fXX 22 8 bit timer counter 5 TM5 8 bit compare register 50 CR50 8 Clear INTTM6 INTTM5 Selector Selector 8 bit timer 6 fXX 29 fXX 27 fXX 25 fXX 24 fXX...

Page 149: ...output The 16 bit timer event counter can output a square wave whose frequency and output pulse width can be freely set 3 Pulse width measurement The 16 bit timer event counter can be used to measure...

Page 150: ...ster 0 TOC0 Prescaler mode register 0 PRM0 Figure 8 1 Block Diagram of 16 Bit Timer Event Counter Internal bus CRC02 CRC01 CRC00 Capture compare control register 0 CRC0 TI01 fXX 4 fXX 16 INTTM3 fXX TI...

Page 151: ...g operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to 0000H in the following cases 1 RESET is input 2 TMC03 and TMC02 are cl...

Page 152: ...re set with prescaler mode register 0 PRM0 Tables 8 2 and 8 3 show the conditions that apply when the capture trigger is specified as the valid edge of the TI00 pin and the valid edge of the TI01 pin...

Page 153: ...ster The valid edge of the TI00 pin can be selected as a capture trigger The valid edge for TI00 is set with prescaler mode register 0 PRM0 Table 8 4 shows the conditions that apply when the capture t...

Page 154: ...Prescaler mode register 0 PRM0 1 16 bit timer mode control register 0 TMC0 This register specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of 16...

Page 155: ...n of interrupt Not affected Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00 match between TM0 and CR01 or valid edge of TI00 Match between TM0 and CR00 or match bet...

Page 156: ...e count value of TM0 changes from FFFFH to 0000H with CR00 set to FFFFH 3 The software trigger bit 6 OSPT of 16 bit timer output control register 0 TOC0 1 and the external trigger TI00 input are alway...

Page 157: ...mode of CR00 0 Operates as compare register 1 Operates as capture register Cautions 1 Before setting CRC0 be sure to stop the timer operation 2 When the mode in which the timer is cleared and started...

Page 158: ...t TOC04 Timer output F F control on match between CR01 and TM0 0 Inversion disabled 1 Inversion enabled LVS0 LVR0 Timer output control by software 0 0 Not affected 0 1 Reset 0 1 0 Set 1 1 1 Setting pr...

Page 159: ...lection of valid edge of TI01 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES01 ES00 Selection of valid edge of TI00 0 0 Falling edge 0 1 Rising edge 1 0 S...

Page 160: ...f CR00 the value of TM0 is cleared to 0 and the timer continues counting At the same time an interrupt request signal INTTM00 is generated The count clock of the 16 bit timer event counter can be sele...

Page 161: ...register 00 CR00 16 bit timer counter 0 TM0 OVF0 Clear circuit INTTM00 Figure 8 8 Timing of Interval Timer Operation Count starts Clear Clear Interrupt acknowledgement Interrupt acknowledgement t 000...

Page 162: ...e compare register 01 CR01 Figure 8 9 Control Register Settings in PPG Output Operation a 16 bit timer mode control register 0 TMC0 0 0 0 0 TMC03 1 TMC02 1 TMC01 0 OVF0 0 TMC0 Clears and starts on mat...

Page 163: ...set The edge is specified by using bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 The rising edge falling edge or both the rising and falling edges can be selected The valid edge is det...

Page 164: ...Running Counter and One Capture Register with Both Edges Specified t D1 D0 t 10000H D1 D2 t D3 D2 t Count clock 0000 0001 D0 D1 0000 D2 D3 TM0 count value D3 TI00 pin input Value loaded to CR01 INTTM0...

Page 165: ...NTTM00 is set The rising falling or both rising and falling edges can be specified for the TI00 P35 and TI01 P36 pins The valid edge of TI00 P35 pin and TI01 P36 pin is detected through sampling at a...

Page 166: ...Free Running Counter with Both Edges Specified t D1 D0 t 10000H D1 D2 t Count clock 0000 0001 D0 D1 FFFF 0000 D2 D3 TM0 count value D0 D1 D2 D3 TI00 pin input Value loaded to CR01 INTTM01 OVF0 D1 100...

Page 167: ...edge of TI00 P35 pin is detected through sampling at a count clock cycle selected by prescaler mode register 0 PRM0 and the capture operation is not performed until the valid level is detected two tim...

Page 168: ...01 D0 D1 FFFF 0000 D2 D3 TM0 count value D0 D2 D3 TI00 pin input Value loaded to CR01 Value loaded to CR00 D1 D3 D2 t INTTM01 OVF0 Caution For simplification purposes delay due to noise elimination is...

Page 169: ...e operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TI00 P35 pin is specified to be both...

Page 170: ...l event counter which counts the number of clock pulses input to the TI00 P35 pin from an external source by using 16 bit timer counter 0 TM0 Each time the valid edge specified by prescaler mode regis...

Page 171: ...re compare control register 0 CRC0 0 0 0 0 0 CRC02 0 1 CRC01 0 1 CRC00 0 CRC0 CR00 as compare register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with...

Page 172: ...event counter 8 4 5 Operation to output square wave The 16 bit timer event counter operates as the square wave output for the user defined frequency that is used as the interval for the count value pr...

Page 173: ...ontrol register 0 TOC0 Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the square wave output function For details refer to Figures 8 2 to 8 4 Figure 8...

Page 174: ...is asserted active at the count value set in advance to 16 bit capture compare register 01 CR01 After that the output is deasserted inactive at the count value set in advance to 16 bit capture compare...

Page 175: ...re register CR01 as compare register c 16 bit timer output control register 0 TOC0 0 OSPT 0 OSPE 1 TOC04 1 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TOC0 Enables TO0 output Sets one shot pulse output mode Set...

Page 176: ...3 M N M N M N N N N 1 M Cautions 1 16 bit timer counter 0 starts operating as soon as a value other than 0 0 operation stop mode has been set to TMC02 and TMC03 2 The software trigger bit 6 OSPT of 16...

Page 177: ...P35 pin is detected the 16 bit timer event counter is cleared and started and the output is asserted active at the count value set in advance to 16 bit capture compare register 01 CR01 After that the...

Page 178: ...R00 as compare register CR01 as compare register c 16 bit timer output control register 0 TOC0 0 OSPT 0 OSPE 1 TOC04 1 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TOC0 Enables TO0 output Sets one shot pulse outp...

Page 179: ...N 1 N 2 M 1 M M N M N M N N M 2 M 1 M 2 M 3 Cautions 1 16 bit timer counter 0 starts operating as soon as a value other than 0 0 operation stop mode has been set to TMC02 and TMC03 2 The software trig...

Page 180: ...ture compare registers 00 and 01 CR00 01 Single pulse counts are consequently not possible for the usage time used as an event counter 3 Operation after changing compare register during timer count op...

Page 181: ...ge The valid edge of the TI00 P35 pin sets 0 0 in bits 2 and 3 of 16 bit timer mode control register 0 TMC0 and this setting should be made the moment timer operations have been halted The valid edge...

Page 182: ...software When a one shot pulse is output do not set OSPT to 1 Do not output the one shot pulse again until INTTM00 which occurs on match between TM0 and CR00 occurs b One shot pulse output with extern...

Page 183: ...01 are used as capture registers The capture trigger input is preceded The read data of CR00 and CR01 is undefined 2 Match timing conflict between the write the period of the 16 bit capture compare re...

Page 184: ...xt 1 Mode using 8 bit timer event counters 1 and 2 alone discrete mode The timer operates as an 8 bit timer event counter It can have the following functions Interval timer External event counter Squa...

Page 185: ...bit timer mode control register 2 TMC2 Prescaler mode register 1 PRM1 Prescaler mode register 2 PRM2 Figure 9 1 Block Diagram of 8 Bit Timer Event Counters 1 and 2 1 2 1 8 bit timer event counter 1 I...

Page 186: ...Internal bus Internal bus TCL22 TCL21 TCL20 Prescaler mode register 2 PRM2 8 bit timer mode control register 2 TMC2 TOE2 TMC26 TMC24 LVS2 LVR2 TMC2 TOE2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 27 fXX 29 TI2 T...

Page 187: ...the cascade connection the count becomes 00H by clearing both bit 7 TCE1 of 8 bit timer mode control register 1 TMC1 and bit 7 TCE2 of 8 bit timer mode control register 2 TMC2 Remark n 1 2 2 8 bit co...

Page 188: ...he following six settings 1 Controls the counting for 8 bit timer counters 1 and 2 TM1 TM2 2 Selects the operation mode of 8 bit timer counters 1 and 2 TM1 TM2 3 Selects the discrete mode or cascade m...

Page 189: ...CR10 match 1 PWM free running mode LVS1 LVR1 Timer output control by software 0 0 No change 0 1 Reset to 0 1 0 Set to 1 1 1 Setting prohibited TMC11 Other than PWM mode TMC16 0 PWM mode TMC16 1 Timer...

Page 190: ...TM1 LVS2 LVR2 Timer output control by software 0 0 No change 0 1 Reset to 0 1 0 Set to 1 1 1 Setting prohibited TMC21 Other than PWM mode TMC26 0 PWM mode TMC26 1 Timer output control Active level se...

Page 191: ...0FF56H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PRM1 0 0 0 0 0 TCL12 TCL11 TCL10 TCL12 TCL11 TCL10 Count clock selection 0 0 0 Falling edge of TI1 0 0 1 Rising edge of TI1 0 1 0 fXX 4 3 13 MHz 0 1...

Page 192: ...ng edge of TI2 0 0 1 Rising edge of TI2 0 1 0 fXX 4 3 13 MHz 0 1 1 fXX 8 1 56 MHz 1 0 0 fXX 16 781 kHz 1 0 1 fXX 32 391 kHz 1 1 0 fXX 128 97 6 kHz 1 1 1 fXX 512 24 4 kHz Cautions 1 If writing data dif...

Page 193: ...alue of TM1 TM2 to 0 and continuing the count the interrupt request signal INTTM1 INTTM2 is generated The TM1 and TM2 count clocks can be selected with bit 0 to 2 TCLn0 to TCLn2 in prescaler mode regi...

Page 194: ...Operation 1 3 a Basic operation Count starts Clear Clear Interrupt request acknowledgement Interrupt request acknowledgement t 00H 01H N 00H 01H N 00H 01H N N N N N Interval time Interval time Interv...

Page 195: ...l Timer Operation 2 3 b When CRn0 00H t Count clock TMn CRn0 TCEn INTTMn TOn Interval time 00H 00H 00H 00H 00H c When CRn0 FFH t Count clock TMn CRn0 TCEn INTTMn TOn 01H FEH FFH 00H FEH FFH 00H FFH FF...

Page 196: ...al Timer Operation 3 3 d Operated by CRn0 transition M N Count clock TMn CRn0 TCEn INTTMn TOn N 00H M N FFH 00H M 00H N H M CRn0 transition TMn overflows since M N e Operated by CRn0 transition M N Co...

Page 197: ...nted The edge setting is selected to be either a rising edge falling edge If the counting of TM1and TM2 matches with the values of 8 bit compare registers 10 and 20 CR10 CR20 the TM1and TM2 are cleare...

Page 198: ...duty cycle 50 is possible Setting method 1 Set the registers Set the port latch which also functions as timer output pin and the port mode register to 0 PRMn Select the count clock CRn0 Compare value...

Page 199: ...ing method 1 Set the port latch which also functions as timer output pin and the port mode register to 0 2 Set the active level width in 8 bit compare register n CRn0 3 Select the count clock in presc...

Page 200: ...01H 02H M 00H N N M N N N Active level Reload Reload Inactive level Active level Count clock TMn CRn0 CRn0 read value TCEn INTTMn TOn 00H 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H 00H 00H M...

Page 201: ...When the CRn0 value changes from N to M after TMn overflows Count clock TMn CRn0 CRn0 read value TCEn INTTMn TOn N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H 03H M M M 1 M 2 CRn0 transit...

Page 202: ...connected in cascade and CRn0 match the INTTM1 of TM1 is generated TM1 and TM2 are cleared to 00H 4 INTTM1 are repeatedly generated at the same interval Cautions 1 Always set the compare register CR1...

Page 203: ...g continues overflows and counting starts again from 0 Consequently when the value M after CR10 CR20 changes is less than the value N before the change the timer must restart after CR10 CR20 changes F...

Page 204: ...bit resolution cascade connection mode These two modes are described next 1 Mode using 8 bit timers 5 and 6 alone discrete mode The timer operates as an 8 bit timer It can have the following function...

Page 205: ...C5 8 bit timer mode control register 6 TMC6 Prescaler mode register 5 PRM5 Prescaler mode register 6 PRM6 Figure 10 1 Block Diagram of 8 Bit Timers 5 and 6 1 2 1 8 bit timer 5 Internal bus Internal bu...

Page 206: ...r 6 Internal bus Internal bus TCL62 TCL61 TCL60 Prescaler mode register 6 PRM6 8 bit timer mode control register 6 TMC6 TOE6 TMC66 TMC64 fXX 22 fXX 23 fXX 24 fXX 25 fXX 27 fXX 29 TI6 TM5 overflow Sele...

Page 207: ...e cascade connection the count becomes 00H by clearing bit 7 TCE5 of 8 bit timer mode control register 5 TMC5 and bit 7 TCE6 of 8 bit timer mode control register 6 TMC6 Remark n 5 6 2 8 bit compare re...

Page 208: ...or 8 bit memory manipulation instruction RESET input sets TMC5 and TMC6 to 00H Figures 10 2 and 10 3 show the TMC5 format and TMC6 format respectively Figure 10 2 Format of 8 Bit Timer Mode Control Re...

Page 209: ...ting TMC66 TM6 operation mode selection 0 Clear and start mode when TM6 and CR60 match 1 PWM free running mode TMC64 Discrete mode or cascade connection mode selection 0 Discrete mode 1 Cascade connec...

Page 210: ...ler Mode Register 5 PRM5 Address 0FF6CH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PRM5 0 0 0 0 0 TCL52 TCL51 TCL50 TCL52 TCL51 TCL50 Count clock selection 0 1 0 fXX 4 3 13 MHz 0 1 1 fXX 8 1 56 MHz 1...

Page 211: ...TCL62 TCL61 TCL60 Count clock selection 0 1 0 fXX 4 3 13 MHz 0 1 1 fXX 8 1 56 MHz 1 0 0 fXX 16 781 kHz 1 0 1 fXX 32 391 kHz 1 1 0 fXX 128 97 6 kHz 1 1 1 fXX 512 24 4 kHz Other than above Setting prohi...

Page 212: ...lue of TM5 TM6 to 0 and continuing the count the interrupt request signal INTTM5 INTTM6 is generated TM5 and TM6 count clocks can be selected with bit 0 to 2 TCLn0 to TCLn2 in prescaler mode registers...

Page 213: ...ration 1 3 a Basic operation Count starts Clear Clear Interrupt request acknowledgement Interrupt request acknowledgement t 00H 01H N 00H 01H N 00H 01H N N N N N Interval time Interval time Interval t...

Page 214: ...Timer Operation 2 3 b When CRn0 00H t Count clock TMn CRn0 TCEn INTTMn Interval time 00H 00H 00H 00H 00H c When CRn0 FFH t Count clock TMn CRn0 TCEn INTTMn 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Inte...

Page 215: ...Timer Operation 3 3 d Operated by CRn0 transition M N Count clock TMn CRn0 TCEn INTTMn N 00H M N FFH 00H M 00H N H M CRn0 transition TMn overflows since M N e Operated by CRn0 transition M N Count cl...

Page 216: ...FH 00H 01H 02H M N 1 N 2 N 02H M H b When the CRn0 value changes from N to M after TMn overflows Count clock TMn CRn0 TCEn INTTMn N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H 03H M M N 1...

Page 217: ...If the values of TMn of all timers connected in cascade and CRn0 match the INTTM5 of TM5 is generated TM5 and TM6 are cleared to 00H 4 INTTM5 are repeatedly generated at the same interval Cautions 1...

Page 218: ...ntinues overflows and counting starts again from 0 Consequently when the value M after CR50 CR60 changes is less than the value N before the change the timer must restart after CR50 CR60 changes Figur...

Page 219: ...kHz subsystem clock to generate the 0 5 second time interval Remark fW Watch timer clock oscillation frequency fXX 27 or fXT fXX Main system clock oscillation frequency fXT Subsystem clock oscillation...

Page 220: ...timer mode control register WTM Figure 11 1 Block Diagram of Watch Timer Selector Selector Selector Internal bus 5 bit counter 9 bit prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW WTM0 INTWT INTTM3...

Page 221: ...l register WTM This register enables or disables the count clock and operation of the watch timer sets the interval time of the prescaler controls the operation of the 5 bit counter and sets the set t...

Page 222: ...f watch flag 0 214 fW 0 5 s 1 25 fW 977 s WTM1 Controls operation of 5 bit counter 0 Clear after operation stop 1 Start WTM0 Controls operation of 5 bit counter 0 Operation stop clear both prescaler a...

Page 223: ...cond time interval 11 4 2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request INTTM3 at intervals specified by a count valu...

Page 224: ...Interval time T nT nT Caution When enabling operation of the watch timer mode control register WTM watch timer and 5 bit counter the time until the first watch timer interrupt request INTWT is genera...

Page 225: ...ut If the watchdog timer overflows without executing the instruction that clears the watchdog timer within the set period a watchdog timer interrupt INTWDT is generated to signal a program error 12 1...

Page 226: ...ress that caused the error can be identified from the return address saved in the stack If returning by simply using the RETB instruction from the operand error an infinite loop results Since an opera...

Page 227: ...1 Watchdog timer interrupt request NMI pin input interrupt request WDT2 WDT1 Count clock Overflow time ms fCLK 12 5 MHz 0 0 fCLK 217 10 5 0 1 fCLK 219 41 9 1 0 fCLK 220 83 9 1 1 fCLK 221 167 8 Cautio...

Page 228: ...ity order The watchdog timer interrupt INTWDT can be specified as either maskable or non maskable according to the interrupt selection control register SNMI setting When writing 0 to bit 1 SWDT of SNM...

Page 229: ...periodically cleared 4 When the watchdog timer is periodically cleared by an instruction group that is executed during program loop 5 When the STOP mode and HALT mode or IDLE mode is the result of in...

Page 230: ...e start Conversion is started by setting the A D converter mode register ADM Select one channel for analog input from ANI0 to ANI7 and perform A D conversion If hardware start is used A D conversion s...

Page 231: ...omparator Tap selector INTAD INTP3 Successive approximation register SAR A D converter input selection register ADIS ADIS2 ADIS1 ADIS0 INTP3 P03 TRG FR2 FR1 FR0 EGA1 EGA0 ADCE A D conversion result re...

Page 232: ...log input channels used for inputting analog data to the A D converter for A D conversion Pins not selected for analog input with the A D convertor input selection register ADIS can be used as input p...

Page 233: ...ters A D converter mode register ADM A D converter input selection register ADIS 1 A D converter mode register ADM Used to set the A D conversion time of analog input to be converted start stop of con...

Page 234: ...r of clocks fXX 12 5 MHz fXX 6 25 MHz 0 0 0 144 fXX Setting prohibited 23 0 s 0 0 1 120 fXX Setting prohibited 19 2 s 0 1 0 96 fXX Setting prohibited 15 4 s 1 0 0 288 fXX 23 0 s 46 1 s 1 0 1 240 fXX 1...

Page 235: ...more When VDD 1 9 V to 2 0 V 48 s or more PD78F4225 only When VDD 1 8 V to 2 0 V 48 s or more PD784224 784225 only 4 If ADCS is set when ADCE 0 the first A D conversion value is undefined Remark fXX M...

Page 236: ...VDD the setting for the SAR MSB will remain the same If it is smaller than 1 2 AVDD the MSB will be reset 6 Next bit 6 of SAR is automatically set and the next comparison is started The series resisto...

Page 237: ...lized and conversion starts from the beginning if the ADCS bit is set 1 RESET input makes A D conversion result register ADCR undefined If bit 0 ADCE of the A D converter mode register is not set to 1...

Page 238: ...ADCR 0 5 VIN ADCR 0 5 Remark INT Function returning the integer portion of the value in parentheses VIN Analog input voltage AVDD AVDD pin voltage ADCR A D conversion result register ADCR value Figure...

Page 239: ...egins The result of conversion will be stored in the A D conversion result register ADCR when A D conversion operation have finished and an interrupt request signal INTAD will be issued When the A D c...

Page 240: ...ANInNote ANIn ANIn ANImNote ANIm ANIn ANIn Standby status Standby status ADM overwrite ADCS 1 TRG 1 ANIm ANIm ANIm Remark n 0 1 7 m 0 1 7 Note If bit 0 ADCE of the A D converter mode register is not s...

Page 241: ...ten to ADM The A D conversion process will be suspended if ADCS is overwritten during A D conversion operations and A D conversion operations for the newly selected analog input channel will be starte...

Page 242: ...ull scale error integral linearity error differential linearity error and combinations of these errors are expressed as the overall error Note that the quantization error is not included in the overal...

Page 243: ...1 110 to 1 111 full scale 3 2LSB 6 Integral linearity error This expresses the extent to which the conversion characteristics differ from the theoretical linear relationship The integral linearity er...

Page 244: ...s obtained The sampling time is included in the conversion time value shown in the characteristic table 9 Sampling time This is the time during which the analog switch is on to allow the analog voltag...

Page 245: ...even if within the absolute maximum rated range will cause the channel s conversion values to become undefined or may affect the conversion values of other channels 3 Contention operation 1 Contentio...

Page 246: ...esolution Moreover if a digital pulse is applied to other analog input pins during A D conversion the A D conversion value will not be obtained as expected because of coupling noise Therefore do not a...

Page 247: ...or not when ADIF is read immediately after ADIS has been overwritten These facts should be kept in mind Moreover if A D conversion is stopped once and then resumed clear ADIF before resuming conversi...

Page 248: ...rter mode register ADM is set to 1 without setting bit 0 ADCE to 1 the value of the first A D conversion is undefined immediately after the A D conversion operation starts Poll the A D conversion end...

Page 249: ...ead the A D conversion result while the A D converter is in operation Furthermore when reading an A D conversion result after the A D converter operation has stopped be sure to have done so by the tim...

Page 250: ...version Be sure to connect a capacitor between the VDD0 and AVDD pins in this case also An example of capacitor connection is shown in Figure 13 20 below Figure 13 20 Example of Capacitor Connection B...

Page 251: ...VDD0 R1 R2 C1 C2 C3 1 8 V 75 k 30 k 3 pF 4 pF 2 pF 2 7 V 12 k 8 k 3 pF 3 pF 2 pF 4 5 V 3 k 2 7 k 3 pF 1 4 pF 2 pF Caution The resistance and capacitance values in Table 13 2 cannot be guaranteed Figur...

Page 252: ...t synchronized to the output trigger Since a sine wave is created when this mode is used MSK modems can be easily incorporated into cordless phones Caution If only one channel of the D A converter is...

Page 253: ...DACS1 DACS0 and DACS1 set the analog voltages that are output to the ANO0 and ANO1 pins respectively DACS0 and DACS1 are set by 8 bit memory manipulation instructions RESET input sets DACS0 and DACS1...

Page 254: ...isters 0 and 1 DAM0 DAM1 Address 0FF86H 0FF87H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 DAMn 0 0 0 0 0 0 DAMn DACEn DAMn D A converter channel n operation mode 0 Normal mode 1 Real time output mode...

Page 255: ...he real time output mode the analog voltage is output synchronized to the output trigger 5 In the normal mode the output analog voltages are maintained until new data are set in DACS0 and DACS1 In the...

Page 256: ...84225Y 2 Output voltages of the D A converters Since the output voltages of the D A converters change in stages use the signals output from the D A converters after passing them through low pass filte...

Page 257: ...Therefore communication outside and within the system can be simultaneous on the three channels Asynchronous serial interface UART 3 wire serial I O IOE 2 channels See CHAPER 16 Clocked serial interfa...

Page 258: ...er receiver PD4711A UART UART Port Port RxD1 TxD1 RxD2 TxD2 SDA0 SCL0 I2 C LCD PD78054Y slave PD78062Y slave VDD0 SDA SCL SDA SCL VDD0 RS 232C driver receiver b UART 3 wired serial I O PD784225Y maste...

Page 259: ...hronous serial interface mode register TXE1 RXE1 PS11 TXE2 RXE2 PS21 PS10 CL1 SL1 PS20 CL2 SL2 ISRM1 ISRM2 Asynchronous serial interface status register ASIS1 ASIS2 Name of bits inside asynchronous se...

Page 260: ...Serial Interface Mode and 3 Wire Serial I O Mode TXE2 RXE2 PS21 PS20 CL2 0FF71H ASIM2 SL2 ISRM2 1 00H R W TXE1 TXE2 0 0 0 1 1 RXE1 RXE2 0 0 1 0 1 Operation stop mode 3 wire serial I O mode TXE1 7 RXE...

Page 261: ...sion at any baud rate within a broad range The baud rate can also be defined by dividing the input clock to the ASCK pin The MIDI specification baud rate 31 25 Kbps can be used by utilizing the UART d...

Page 262: ...nternal bus INTST1 INTST2 Transmit control parity addition Receive buffer registers 1 2 RXB1 RXB2 Receive shift registers 1 2 RX1 RX2 Receive control parity check RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 INTSR...

Page 263: ...rs 1 2 RXB1 RXB2 These registers are used to hold receive data Each time one byte of data is received new receive data is transferred from receive shift registers 1 2 RX1 RX2 If a data length of 7 bit...

Page 264: ...de registers 1 2 ASIM1 ASIM2 Asynchronous serial interface status registers 1 2 ASIS1 ASIS2 Baud rate generator control registers 1 2 BRGC1 BRGC2 1 Asynchronous serial interface mode registers 1 2 ASI...

Page 265: ...1 UART mode Serial function Serial function Transmit Receive PSn1 PSn0 Parity bit specification 0 0 No parity 0 1 Always add 0 parity during transmission Do not perform parity check during reception...

Page 266: ...flag 0 Framing error not generated 1 Framing error generatedNote 1 when stop bit s is not detected OVEn Overrun error flag 0 Overrun error not generated 1 Overrun error generatedNote 2 When next rece...

Page 267: ...17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK...

Page 268: ...rface mode registers 1 and 2 ASIM1 ASIM2 ASIM1 and ASIM2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM1 and ASIM2 to 00H Address 0FF70H 0FF71H After reset 00H R W S...

Page 269: ...UART dedicated baud rate generator is incorporated enabling communication using any baud rate within a large range The MIDI standard s baud rate 31 25 Kbps can be used utilizing the UART dedicated bau...

Page 270: ...only 1 0 UART mode Port function Serial function Transmit only 1 1 UART mode Serial function Serial function Transmit Receive PSn1 PSn0 Parity bit specification 0 0 No parity 0 1 Always add 0 parity...

Page 271: ...ansmit data does not match FEn Framing error flag 0 Framing error not generated 1 Framing error generatedNote 1 when stop bit s is not detected OVEn Overrun error flag 0 Overrun error not generated 1...

Page 272: ...z 5 1 1 1 TO1 TM1 output 0 MDLn3 MDLn2 MDLn1 MDLn0 Baud rate generator k input clock selection 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21...

Page 273: ...5 bit counter 4 m Value set in TPSn0 to TPSn2 0 m 5 5 k Value set in MDLn0 to MDLn3 0 k 14 The transmit receive clock for the baud rate to be generated is the signal obtained by dividing the 5 bit cou...

Page 274: ...4 19200 54H 1 73 44H 1 73 34H 2 34 31250 49H 0 00 39H 0 00 28H 0 00 38400 44H 1 73 34H 1 73 24H 2 34 76800 34H 1 73 24H 1 73 14H 2 34 150K 24H 1 73 14H 1 73 300K 14H 1 73 Remark When TM1 output is use...

Page 275: ...bits 0 to 6 are valid In the case of transmission the most significant bit bit 7 is ignored In the case of reception the most significant bit bit 7 always becomes 0 The setting of the serial transfer...

Page 276: ...r of 1 bits in receive data that includes the parity bit is counted and if it is odd a parity error occurs ii Odd parity During transmission Odd parity is the reverse of even parity It makes the numbe...

Page 277: ...nsmission output a high level from the TXDn pin 3 Set the port to the output mode PM21 0 or PM71 0 4 Write transmit data to TXSn and start transmission If the port is set to the output mode first 0 wi...

Page 278: ...bit are detected reception of one frame of data is completed When reception of one frame of data is completed the receive data in the shift register is transferred to receive shift register n RXBn and...

Page 279: ...ceived If the next data has an error this error flag is set Remark n 1 2 Table 16 4 Receive Error Causes Receive Error Cause ASISn Parity error Parity specified for transmission and parity of receive...

Page 280: ...e immediately before the clock stops If the clock stops STOP mode during transmission the TxDn pin output data immediately before the clock stopped is held If the clock stops during reception receive...

Page 281: ...processing time The start bit of 8 bit data for serial transfer is fixed as the MSB The 3 wire serial I O mode is effective when connecting a peripheral I O with an on chip clock synchronization seria...

Page 282: ...CSIMn is 1 serial operation can be started by writing reading data to from SIOn During transmission data written to SIOn is output to the serial output pin SOn During reception data is read into SIOn...

Page 283: ...ion enable disable setting Shift register operation Serial counter Port 0 Operation disabled Clear Port functionNote 1 Operation enabled Counter operation Serial function port enabled function MODEn T...

Page 284: ...ial operation registers 1 and 2 CSIM1 CSIM2 CSIM1 and CSIM2 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 and CSIM2 to 00H Figure 16 13 Format of Serial Operati...

Page 285: ...0FF92H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 CSIEn SIOn operation enable disable setting Shift register operation Serial counter Port 0 Operation disabled Cl...

Page 286: ...latched to SIOn at the rising edge of the SCKn signal SIOn operation is automatically stopped when 8 bit transfer ends and an interrupt request flag SRIFn is set Remark n 1 2 Figure 16 15 3 Wire Seri...

Page 287: ...tarting bit of the 8 bit data to be serially transferred is fixed at the MSB The 3 wire serial I O mode is valid when the peripheral I O or display controller with an internal clocked serial interface...

Page 288: ...d serially communication shift operation synchronized to the serial clock SIO0 is set by an 8 bit memory manipulation instruction When bit 7 CSIE0 in serial operation mode register 0 CSIM0 is one seri...

Page 289: ...function MODE0 Transfer operation mode flag Operation mode Transfer start trigger SO0 output 0 Transmit receive SIO0 write Normal output communication mode 1 Receive only mode SIO0 read Fixed low SCL0...

Page 290: ...ode is set in serial operation mode register 0 CSIM0 CSIM0 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Figure 17 3 Format of Serial Operation Mode Register...

Page 291: ...r Port functionNote 1 Operation enabled Operation count enabled Serial function port function MODE0 Transfer operation mode flag Operation mode Transfer start trigger SO0 output 0 Transmit receive SIO...

Page 292: ...ng 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transfer ends Start transfer synchronized to the falling edge of SCK0 SCK0 SI0 SO0 CSIIF0 c Start transfer If the fol...

Page 293: ...slaves The slaves automatically detect the received data by hardware The I2C bus control portion of the application program can be simplified by using this function Since SCL0 and SDA0 become open dr...

Page 294: ...L0 SDA0 SCL0 SDA0 SCL0 VDD0 Master CPU 2 Slave CPU 3 18 2 Configuration The clocked serial interface in the I2C bus mode includes the following hardware Figure 18 2 is a block diagram of clocked seria...

Page 295: ...rator Serial clock counter Serial clock controller Serial clock wait controller Prescaler mode register 0 for the serial clock SPRM0 Noise eliminator SCL0 N ch open drain output Internal bus fXX CL1 C...

Page 296: ...is selects the sampling clock that is used 6 Serial clock counter The serial clock that is output or input during transmission or reception is counted to check 8 bit data communication 7 Interrupt req...

Page 297: ...register 0 IICS0 Prescaler mode register 0 for the serial clock SPRM0 The following registers are also used Serial shift register 0 IIC0 Slave address register 0 SVA0 1 I2C bus control register 0 IIC...

Page 298: ...igh impedance state The following flags are cleared STD0 ACKD0 TRC0 COI0 EXC0 MSTS0 STT0 SPT0 Until the following communication participation conditions are satisfied the wait state that was released...

Page 299: ...ress transfer and becomes valid after the transfer ends In the master a wait is inserted at the falling edge of the ninth clock in an address transfer The slave that received the base address inserts...

Page 300: ...the bus is released Wait status when master The wait status is canceled and the restart condition is generated Cautions on set timing Master reception Setting is prohibited during transfer STT0 can b...

Page 301: ...ock is output the stop condition is generated during the high level of the ninth clock after the wait is released When the ninth clock must be output set WTIM0 0 1 during the wait period after the eig...

Page 302: ...enerated When ALD0 1 Cleared by LREL0 1 When IICE0 1 0 When RESET is input ALD0 Arbitration failed detection 0 No arbitration state or arbitration win state 1 Arbitration failed state MSTS0 is cleared...

Page 303: ...the SO latch can be output to the SDA0 line valid after the falling edge of the ninth clock of the first byte Clear condition TRC0 0 Set condition TRC0 1 When the stop condition is detected In the ma...

Page 304: ...s indicates the address transfer period Clear condition STD0 0 Set condition STD0 1 When the stop condition is detected When the start condition is detected At the rising edge of the first clock of th...

Page 305: ...ter reset 00H R WNote Symbol 7 6 5 4 3 2 1 0 SPRM0 0 0 CLD DAD SMC DFC CL1 CL0 CLD SCL0 line level detection valid only when IICE0 1 0 Detects a low SCL0 line 1 Detects a high SCL0 line Clear conditio...

Page 306: ...s in high speed mode 2 DFC Bit to control digital filter operation 0 Digital filter off 1 Digital filter on Cautions 1 Rewrite the SPRM0 after clearing the IICE0 2 Set the transfer clock as follows Wh...

Page 307: ...Although this register can be read and written in 1 bit and 8 bit units do not write data to IIC0 during a data transfer Address 0FFB8H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IIC0 5 Slave address...

Page 308: ...slave are N ch open drains The input is a Schmitt input 2 SDA0 Shared I O pin for serial data The outputs to both the master and slave are N ch open drains The input is a Schmitt input Since the outp...

Page 309: ...n be output by either the master or slave Normally this is output on side receiving 8 bit data The serial clock SCL0 continues to the master output However the slave can extend the SCL0 low level peri...

Page 310: ...extended code was received during slave operation INTIIC0 is not generated The address is output by matching the slave address and matching the transfer direction described in 18 5 3 Transfer directi...

Page 311: ...signal state is entered Bit 3 TRC0 in I2C bus status register 0 IICS0 is set by the data in the eighth bit following the 7 bit address information However set ACKE0 1 in the reception state when TRC0...

Page 312: ...signal output by the master to the slave when serial transfer ends The slave has hardware that detects the stop condition Figure 18 12 Stop Condition H SDA0 SCL0 The stop condition is generated when b...

Page 313: ...aster and the slave are released from the wait state the next transfer can start Figure 18 13 Wait Signal 1 2 1 The master has a 9 clock wait and the slave has an 8 clock wait Master transmission Slav...

Page 314: ...D1 6 7 8 9 1 2 3 D0 ACK D6 D5 ACKE0 H D7 Output in accordance with the preset ACKE0 1 Remark ACKE0 Bit 2 in I2C bus control register 0 IICC0 WREL0 Bit 5 in I2C bus control register 0 IICC0 A wait is a...

Page 315: ...ion a Start Address Data Data Stop normal communication 1 When WTIM0 0 1 2 3 5 RW AK AD6 to AD0 AK SPT0 1 SP D7 to D0 AK D7 to D0 ST 4 1 IICS0 10 110B 2 IICS0 10 000B 3 IICS0 10 000B WTIM0 1 4 IICS0 1...

Page 316: ...10 110B 2 IICS0 10 000B WTIM0 1 3 IICS0 10 00B WTIM0 0 4 IICS0 10 110B WTIM0 0 5 IICS0 10 000B WTIM0 1 6 IICS0 10 00B 7 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care...

Page 317: ...D7 to D0 ST 4 SPT0 1 1 IICS0 1010 110B 2 IICS0 1010 000B 3 IICS0 1010 000B WTIM0 1 4 IICS0 1010 00B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 1 2...

Page 318: ...3 4 RW AK AD6 to AD0 AK SP D7 to D0 AK D7 to D0 ST 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0...

Page 319: ...to D0 ST 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 SVA0 match after rest...

Page 320: ...IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 extended code received after res...

Page 321: ...D6 to AD0 SP AK D7 to D0 ST 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 00000 10B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 no address match afte...

Page 322: ...D0 AK SP D7 to D0 AK D7 to D0 ST 1 1 IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 5 RW AK AD6 to...

Page 323: ...IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 SVA0 match after restart 3 4 5 6...

Page 324: ...010B 2 IICS0 0010 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 extended code received after restart 3 5 6 7...

Page 325: ...01B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 no address match after restart not an extended code 3 4 5 RW AK AD6 to AD0 AK D7 to D0 ST RW AK AD6 to AD0 SP AK D7 t...

Page 326: ...SP D7 to D0 AK D7 to D0 ST 1 2 3 1 IICS0 0101 110B Example Read ALD0 during interrupt servicing 2 IICS0 0001 000B 3 IICS0 0001 000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE0...

Page 327: ...xample Read ALD0 during interrupt servicing 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care 2 When WTIM0 1 1 2 3 5 4 RW AK AD6 to...

Page 328: ...D7 to D0 AK D7 to D0 ST 1 IICS0 01000110B Example Read ALD0 during interrupt servicing 2 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 b When arbitration failed while transmitti...

Page 329: ...D7 to D0 ST 1 IICS0 10001110B 2 IICS0 01000000B Example Read ALD0 during interrupt servicing 3 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 2 When WTIM0 1 1 2 3 RW AK AD6 to AD...

Page 330: ...IICS0 1000 110B 2 IICS0 01000110B Example Read ALD0 during interrupt servicing 3 IICS0 00000001B Remarks Always generated Generated only when SPIE0 1 don t care Dn D6 to D0 2 Extended code 1 2 3 RW A...

Page 331: ...was about to be generated WTIM0 1 1 2 3 STT0 1 4 RW AK AD6 to AD0 D7 to D0 ST AK SP AK D7 to D0 AK D7 to D0 1 IICS0 1000 110B 2 IICS0 1000 00B 3 IICS0 01000100B Example Read ALD0 during interrupt ser...

Page 332: ...ta level and the stop condition was about to be generated WTIM0 1 1 2 3 SPT0 1 4 RW AK AD6 to AD0 D7 to D0 ST AK SP AK D7 to D0 AK D7 to D0 1 IICS0 1000 110B 2 IICS0 1000 00B 3 IICS0 01000000B Example...

Page 333: ...t generated Remark The numbers in the table indicate the number of clocks in the serial clock In addition the interrupt request and wait control are both synchronized to the falling edge of the serial...

Page 334: ...ter 0 SVA0 if the slave address transmitted from the master matches the address set in SVA0 or if the extended code is received an INTIIC0 interrupt request occurs 18 5 10 Error detection In the I2C b...

Page 335: ...after an extended code is received enter the next communication wait state by setting bit 6 LREL0 1 of I2C bus control register 0 IICC0 Table 18 3 Definitions of Extended Code Bits Slave Address R W...

Page 336: ...r Stop condition detection during data transfer When stop condition is output SPIE0 1 Note 2 Data is low when the restart condition is about to be Falling edge of clock 8 or 9 after byte transferNote...

Page 337: ...not generated and efficient processing is possible When the start condition is detected the wake up standby function is entered Since the master can become a slave in an arbitration failure when a sta...

Page 338: ...it state is entered When the bus release is detected stop condition detection the address transfer starts as the master by the write operation of serial shift register 0 IIC0 In this case set bit 4 SP...

Page 339: ...ttings Output from the master that possessed the bus IIC0 Serial shift register STT0 Bit 1 in I2C bus control register 0 IICC0 STD0 Bit 1 in I2C bus status register 0 IICS0 SPD0 Bit 0 in I2C bus statu...

Page 340: ...2C bus control register 0 IICC0 MSTS0 Bit 7 in I2C bus status register 0 IICS0 IIC0 Serial shift register 0 DI SET1 STT0 Define communication reservation Communication reservation is released MOV IIC0...

Page 341: ...t released perform master communication after the stop condition is first generated and the bus is released The master cannot communicate in the state where the bus is not released the stop condition...

Page 342: ...art IIC0 write transfer IICC0 H IICE0 SPIE0 WTIM0 1 STT0 1 INTIIC0 1 INTIIC0 1 Start IIC0 write transfer Stop condition generation No slave with address match INTIIC0 1 ACKD0 1 ACKD0 1 TRC0 1 START Ye...

Page 343: ...ve Operating Procedure IICC0 H IICE0 1 INTIIC0 1 EXC0 1 INTIIC0 1 ACKD0 1 COI0 1 TRC0 1 START Yes No No Yes Yes No Yes No Yes No Yes No No Yes No Data processing WTIM0 0 ACKE0 1 WREL0 1 Start receptio...

Page 344: ...I2C bus status register 0 IICS0 that indicates the transfer direction of the data after the slave address and starts serial communication with the slave Figures 18 20 and 18 21 are the timing charts f...

Page 345: ...0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H L H H H L L L L Receive Send 1 A6 Start condition A5...

Page 346: ...SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 SCL0 SDA0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H H L L L L L H H L L L L L L H Send Receive Note Note IIC0 Data Mas...

Page 347: ...IIC0 FFH or setting WREL0 IIC0 Data IIC0 FFHNote IIC0 FFHNote Note Note IIC0 Address IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS...

Page 348: ...ddress IIC0 FFHNote IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L H H L L L L Note H H 1 A6 A5 A4...

Page 349: ...0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L L H H H L L L L L H H L L L L H Send Note Note Receive...

Page 350: ...STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H H H L L L Note 1 D7 A6 A5 D6 D5 D4 D3 D2 D1 D0 N ACK IIC0 FF...

Page 351: ...below 1 Select the output frequency of the clock pulse while clock pulse output is disabled with bits 0 to 3 CCS0 to CCS3 2 Set 0 in output latch P23 3 Set bit 3 PM23 of the port mode register PM2 to...

Page 352: ...circuit PCL P23 Clock output control register CKS fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 4 fXX fXT fXX 2 fXX 22 Port 2 mode register PM2 PM23 P23 output latch Selector 19 3 Control Registers The followin...

Page 353: ...ol 0 Clock output stop 1 Clock output start CCS3 CCS2 CCS1 CCS0 Clock output frequency selection 0 0 0 0 fXX 12 5 MHz 0 0 0 1 fXX 2 6 25 MHz 0 0 1 0 fXX 4 3 13 MHz 0 0 1 1 fXX 8 1 56 MHz 0 1 0 0 fXX 1...

Page 354: ...tput set the output latch of PM23 and P23 to 0 PM2 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 19 4 Format of Port 2 Mode Register PM2 Address 0FF22H...

Page 355: ...ibited from sounding 2 Set the P24 output latch to 0 3 Set bit 4 PM24 of the port 2 mode register PM2 to 0 set the output mode Caution When the output latch of P24 is set to one the buzzer output cann...

Page 356: ...for the buzzer output frequency setting Figure 20 2 Format of Clock Output Control Register CKS Address 0FF40H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKS BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZ...

Page 357: ...ction set the output latches of PM24 and P24 to 0 PM2 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 20 3 Format of Port 2 Mode Register PM2 Address 0FF2...

Page 358: ...and EGN0 registers specify the valid edge to be detected by the P00 to P05 pins They can read write with an 8 bit manipulation instruction or a bit manipulation instruction RESET input sets EGP0 and E...

Page 359: ...oller P00 to P05 output mode during output mode P00 to P05 21 2 Edge Detection of P00 to P05 Pins The P00 to P05 pins do not incorporate an analog delay based noise eliminator Therefore a valid edge i...

Page 360: ...ce Modes Interrupt Request Servicing Performed PC PSW Contents Service Service Mode Vectored interrupts Software Saving to restoration Executed by branching to service program at from stack addressNot...

Page 361: ...Priority Generating Source Unit Register Switching Service Control Table Request Name Word Address Address Software None BRK instruction execution Not Not 003EH possible possible BRKCS instruction ex...

Page 362: ...r end clocked 10 INTST1 ASI1 UART transmission end serial interface 1 STIC1 0FE1CH 001CH 11 INTSER2 ASI2 UART reception error Asynchronous SERIC2 0FE1EH 001EH 12 INTSR2 ASI2 UART reception end serial...

Page 363: ...skable interrupt is generated by NMI pin input or the watchdog timer Non maskable interrupts are acknowledged unconditionallyNote even in the interrupt disabled state They are not subject to interrupt...

Page 364: ...diation of the CPU it is not necessary to save or restore CPU statuses such as the program counter PC and program status word PSW contents This is therefore very effective in improving the CPU service...

Page 365: ...interrupt request Associated MK1 MK1L MK1H with mask control flag in interrupt control register Can be accessed in word or byte units In service priority register ISPR Records priority of interrupt r...

Page 366: ...SM0 CSIPR00 CSICSE0 INTCSI0 CSIPR01 8 INTSER1 SERIC1 SERIF1 SERMK1 SERISM1 SERPR10 SERCSE1 SERPR11 9 INTSR1 SRIC1 SRIF1 SRMK1 SRISM1 SRPR10 SRCSE1 INTCSI1 SRPR11 10 INTST1 STIC1 STIF1 STMK1 STISM1 STP...

Page 367: ...ing since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing This flag can be manipulated bit wise by software RESET input sets all bits to 0 3 Macro...

Page 368: ...xxPRn1 0 0 1 1 xxPRn0 0 1 0 1 CSIMK0 CSIISM0 CSICSE0 0 0 CSIPR01 CSIPR00 Priority 3 Address 0FFE0H to 0FFE6H 0FFE8H R W After reset 43H Symbol Interrupt request generation No interrupt request Interru...

Page 369: ...1 TMPR000 TMIF01 xxIFn 0 1 xxMKn 0 1 xxISMn 0 1 xxCSEn 0 1 xxPRn1 0 0 1 1 xxPRn0 0 1 0 1 TMMK01 TMISM01 TMCSE01 0 0 TMPR011 TMPR010 Priority 3 Address 0FFE9H to 0FFF1H R W After reset 43H Symbol Inter...

Page 370: ...0 1 xxPRn1 0 0 1 1 xxPRn0 0 1 0 1 Address 0FFF2H to 0FFF6H 0FFF9H R W After reset 43H Symbol Priority 3 Interrupt request generation No interrupt request Interrupt signal is not generated Interrupt r...

Page 371: ...uction in 1 bit units Each interrupt mask flag controls enabling disabling of the corresponding interrupt request When an interrupt mask flag is set 1 acknowledgment of the corresponding interrupt req...

Page 372: ...n 0 1 Address 0FFACH to 0FFAFH R W After reset FFH Symbol Interrupt request enable disable Interrupt servicing enabled Interrupt servicing disabled MK0 1 15 14 13 12 11 10 9 TMMK3 PMK5 PMK4 PMK3 PMK2...

Page 373: ...he ISPR that corresponds to the highest priority interrupt request is automatically cleared 0 by hardware The contents of the ISPR are not changed by execution of an RETB or RETCSB instruction RESET i...

Page 374: ...led state DI state should be set first to prevent misoperation IMC can be read or written to with an 8 bit manipulation instruction or bit manipulation instruction RESET input sets the IMC register to...

Page 375: ...op will result As an operand error interrupt is only generated in the event of an inadvertent program loop with the NEC assembler RA78K4 only the correct dedicated instruction is generated when MOV WD...

Page 376: ...0 0 0 0 SWDT 0 SNMI SWDT 0 1 SNMI 0 1 Use as NMI Interrupt servicing cannot be disabled with interrupt mask register At this time release of the standby mode with the P02 pin is accomplished with NMI...

Page 377: ...ruction is executed PSWL is saved to the stack and the IE flag is cleared 0 PSWL is also saved to the stack by the PUSH PSW instruction and is restored from the stack by the RETI RETB and POP PSW inst...

Page 378: ...software interrupt Caution The RETI instruction must not be used to return from a BRK instruction software interrupt 22 4 2 BRKCS instruction software interrupt software context switching acknowledgme...

Page 379: ...ction does not match the 4th byte of the operand Operand error interrupts cannot be disabled When an operand error interrupt is generated the program status word PSW and the start address of the instr...

Page 380: ...0 the in service priority register ISPR bit corresponding to the acknowledged non maskable interrupt is set 1 the vector table contents are loaded into the PC and a branch is performed The ISPR bit th...

Page 381: ...uring NMI service program execution Main routine NMI request NMI request NMIS 1 NMI request held pending since NMIS 1 Pending NMI request is serviced b When a watchdog timer interrupt request is gener...

Page 382: ...the WDM 0 d When an NMI request is generated twice during NMI service program execution Main routine NMI request Watchdog timer interrupt request Watchdog timer interrupt is kept pending because WDT4...

Page 383: ...upt service program execution except when a high non maskable interrupt request is generated during execution of a low priority non maskable interrupt service program and for a certain period after ex...

Page 384: ...hing an interrupt is acknowledged in the interrupt enabled state when the IE flag is set 1 if the priority of that interrupt is one for which acknowledgment is permitted If maskable interrupt requests...

Page 385: ...rupt requests Highest default priority among interrupt requests of same priority Vectored interrupt generation Interrupt request Yes No Interrupt mask released Yes No Yes Yes Yes Yes No No Interrupt e...

Page 386: ...instruction is used 22 7 2 Context switching Initiation of the context switching function is enabled by setting 1 the context switching enable flag of the interrupt control register When an interrupt...

Page 387: ...gram start address must be in the base area Caution The RETCS instruction must be used to return from an interrupt serviced by context switching Subsequent interrupt acknowledgment will not be perform...

Page 388: ...ests for which multiple interruption is permitted are shown in Table 22 5 Since the IE flag is cleared 0 automatically when an interrupt is acknowledged when multiple interruption is used the IE flag...

Page 389: ...servicing g servicing h servicing Since interrupt request b has a higher priority than interrupt request a and interrupts are enabled interrupt request b is acknowledged The priority of interrupt requ...

Page 390: ...disabling and priority The interrupt request is held peding since it has a lower priority than interrupt request k Interrupt request m generated after interrupt request l has a higher priority and is...

Page 391: ...yNote 1 Level 2 Multiple acknowledgment of levels 3 to 0 If the PRSL bit of the IMC register is set 1 only macro service requests and non maskable interrupts generate nesting beyond this If the PRSL...

Page 392: ...ng Interrupt request d servicing Interrupt request e servicing Interrupt request a servicing When requests are generated simultaneously they are acknowledged in order starting with macro service Macro...

Page 393: ...rrupt request fNote 2 Level 3 f servicing e servicing IMC 80H EI Main routine IMC 00H EI Main routine EI EI The PRSL bit of the IMC is set to 1 and nesting between level 3 interrupts is disabled Even...

Page 394: ...ied Figure 22 17 Differences Between Vectored Interrupt and Macro Service Processing Macro service Context switchingNote 1 Vectored interruptNote 1 Vectored interrupt Interrupt request generation Main...

Page 395: ...SI2 UART reception end serial interface 0FE20H INTCSI2 CSI2 3 wire transfer end clocked serial 13 INTST2 ASI2 UART transmission end interface 2 0FE22H 14 INTTM3 Reference time interval signal from wat...

Page 396: ...the macro service channel the entire 1 MB memory space can be used This is a general version of type A suitable for large volumes of transfer data 3 Type C Data is transferred from memory to two spec...

Page 397: ...0 Interrupt request flag 0 Yes No Yes Macro service processing execution Data transfer real time output port control Decrement macro service counter MSC Interrupt request generation Execute next inst...

Page 398: ...ervice mode register for each macro service 1 When VCIE bit is 0 In this mode an interrupt is generated as soon as the macro service ends Figure 22 18 shows an example of macro service and interrupt a...

Page 399: ...of macro service Other interrupt request Last macro service request Servicing of other interrupt Macro service processing Servicing of interrupt request due to end of macro service At the end of macr...

Page 400: ...lowing cases Clocked serial interface receive data transfers INTCSI0 INTCSI1 INTCSI2 Asynchronous serial interface data transfers INTST1 INTST2 To stop a stepping motor in the case INTTM1 INTTM2 of st...

Page 401: ...ro service mode register and the macro service channel address is indicated by the macro service channel pointer The macro service mode register and macro service channel pointer are mapped onto the p...

Page 402: ...Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Chann...

Page 403: ...MOD0 3 CHT3 2 CHT2 1 CHT1 0 CHT0 CHT0 0 1 0 CHT1 0 0 0 CHT2 0 0 0 CHT3 1 0 0 MOD2 MOD1 MOD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 VCIE 0 1 Type A Counter Mode Counter decrement Data transfer...

Page 404: ...rol Ring control No ring control Ring control Data size for timer specified by MPT 2 bytes No automatic addition Automatic addition VCIE 0 1 Generated Not generated next interrupt servicing is vectore...

Page 405: ...ed in the macro service channel With type A the data transfer direction can be selected as memory to SFR or SFR to memory Data transfers are performed the number of times set beforehand in the macro s...

Page 406: ...nts n Calculate buffer addressNote Read SFR pointer contents Determine transfer direction SFR Memory Memory SFR Read buffer contents then transfer read data to specified SFR Specified SFR contents the...

Page 407: ...ATION 0H instruction is executed or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed which is the transfer source or transfer destination refer to Figure 22 24 In the channel pointer the...

Page 408: ...her addresses Lower addresses Macro service buffer address channel pointer macro service counter 1 MSC 1 MSC 2 MSC n b 2 byte transfers 7 0 Macro service counter MSC SFR pointer SFRP Macro service buf...

Page 409: ...emark Addresses in the figure are the values when the LOCATION 0H instruction is executed When the LOCATION 0FH instruction is executed 0F0000H should be added to the values in the figure Internal RAM...

Page 410: ...ry to SFR or SFR to memory Data transfers are performed the number of times set beforehand in the macro service counter One macro service processing transfers 8 bit or 16 bit data This type of macro s...

Page 411: ...Memory SFR SFR Memory MSC MSC 1 MSC 0 No Yes Clear 0 interrupt service mode bit ISM VCIE 1 Vectored interrupt request generation TYPE B Yes No Increment MPNote Read data from SFR and write to memory...

Page 412: ...esses 0FE00H to 0FEFFH when the LOCATION 0H instruction is executed or 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is executed The macro service channel is indicated by the channel pointer as...

Page 413: ...ice control word macro service channel Internal RAM 0FE6EH Buffer area Note Lower 8 bits of port 3 address 1 1 Internal bus Port 3 P37 P36 P35 P34 P33 P32 P31 P30 INTP4 Edge detection Macro service re...

Page 414: ...CHAPTER 22 INTERRUPT FUNCTIONS 414 User s Manual U12697EJ3V0UM Figure 22 29 Parallel Data Input Timing INTP4 Port 3 Data fetch macro service...

Page 415: ...e register of the macro service control word a Updating of timer macro service pointer It is possible to choose whether the timer macro service pointer MPT is to be kept as it is or incremented decrem...

Page 416: ...To other macro service processing Note Transfer data to compare register Automatic addition specified No Increment MPT No Increment MPD TYPE C Yes Read memory addressed by MPT Retain MPT No Increment...

Page 417: ...MSC 0 VCIE 1 Subtract modulo register contents from data macro service pointer MPD and return pointer to start address Add modulo register contents to data macro service pointer MPD and return pointer...

Page 418: ...the pattern when ring control is used When initialization is performed the same value as in the MR is normally set in this counter The macro service counter MSC is a 16 bit counter that specifies the...

Page 419: ...o 15 Bits 8 to 15 Bits 0 to 7 Bits 0 to 7 Bits 16 to 23 Note Bits 16 to 23 Note Channel pointer Mode register Timer macro service pointer MPT Data macro service pointer MPD Data SFR pointer DSFRP Macr...

Page 420: ...ervice pointer MPD Modulo register MR Macro service control word Lower addresses Macro service channel Higher addresses TSFR DSFR Timer buffer area Data buffer area Macro service buffer address macro...

Page 421: ...channel Internal RAM Timer counter 1 TM1 Output latch P120 0FE5EH 123408H 123400H Output data area Lower 8 bits of CR10 address Type C MPT MPD incremented 1 byte timer data no automatic addition no r...

Page 422: ...12697EJ3V0UM Figure 22 33 Data Transfer Control Timing TM1 Count value Count starts 0H Compare register CR10 T1 Buffer register RTBL INTTM1 Timer interrupt P120 P122 P123 P121 T1 T7 T8 T9 D1 D2 D3 D4...

Page 423: ...e only and the one cycle data patterns are output repeatedly in order in ring form When ring control is used only the output patterns for one cycle need be prepared allowing the size of the data ROM a...

Page 424: ...igure 22 34 Single Phase Excitation of 4 Phase Stepper Motor Phase A Phase B Phase C Phase D 1 cycle 4 patterns 1 2 3 4 1 2 3 Figure 22 35 1 2 Phase Excitation of 4 Phase Stepper Motor Phase A Phase B...

Page 425: ...rd macro service channel Internal RAM 16 bit capture compare register 00 CR00 16 bit timer counter 0 TM0 External connection Addition Buffer register RTBL Output latch P120 P120 P122 P121 P123 0FE5AH...

Page 426: ...h 1 2 Phase Excitation TM1W Count value 0H FFFFH Compare register CR1W Buffer register RTBL INTP2 TO0 t1 t P120 P122 P123 P121 t3 t4 t5 t6 t9 T0 T1 T2 T3 T4 T5 T6 T7 t7 t8 D1 D2 D3 D4 D5 D6 D7 D0 D0 D...

Page 427: ...e control word Macro service channel Internal RAM 16 bit capture compare register 00 CR00 16 bit timer counter 0 TM0 Addition Buffer Register RTBL Output latch P120 P120 P122 P121 P123 0FE7AH 123007H...

Page 428: ...ion Constant Velocity Operation TM0 Count value 0H FFFFH Compare register CR10 T0 Buffer register RTBL D6 D5 D4 D3 D2 D1 D0 D7 D6 D7 D0 INTTP2 TO0 t P120 P122 P123 P121 Count starts T1 T2 T3 T4 T5 T6...

Page 429: ...vent counter where the interrupt generation cycle is long Figure 22 40 Macro Service Data Transfer Processing Flow Counter Mode Macro service request acknowledgement End End Reads contents of macro se...

Page 430: ...ddresses Channel pointer Mode register 7 0 3 Example of using counter mode Here is an example of counting the number of edges input to external interrupt pin INTP5 Figure 22 42 Counting Number of Edge...

Page 431: ...istersNote MK0 MK1 IMC ISPR and SNMI PSW bit manipulation instruction Excluding the BT PSWL bit addr20 instruction BF PSWL bit addr20 instruction BT PSWH bit addr20 instruction BF PSWH bit addr20 inst...

Page 432: ...generated by hardware The generated interrupt request sets 1 an interrupt request flag When the interrupt request flag is set 1 a time of 8 clocks 0 64 s fXX 12 5 MHz is taken to determine the priori...

Page 433: ...M internal high speed RAM EMEM internal ROM when external memory and high speed fetch are not specified 2 n is the number of wait states per byte necessary for writing data to the stack the number of...

Page 434: ...ter mode MSC 0 17 USC 0 25 Remarks 1 IRAM Internal high speed RAM 2 In the following cases in the other data areas add the number of clocks specified below If the data size is 2 bytes with IROM or PRA...

Page 435: ...ay of performing initialization by hardware is by RESET input Example MOVW MK0 0FFFFH Mask all maskable interrupts MOV MK1L 0FFH IRESL CMP ISPR 0 No interrupt service programs running BZ NEXT MOVG SP...

Page 436: ...macro service generation 8 The RETI instruction must be used to return from a non maskable interrupt Subsequent interrupt acknowledg ment will not be performed normally if a different instruction is u...

Page 437: ...SW bit manipulation instructions excluding BT PSWL bit addr20 instruction BF PSWL bit addr20 instruction BT PSWH bit addr20 instruction BF PSWH bit addr20 instruction SET1 CY instruction NOT1 CY instr...

Page 438: ...ions in External Memory Expansion Mode Pin Functions When External Device Connected Alternate Name Function Functions AD0 to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Middle address bus P5...

Page 439: ...7 6 5 4 3 2 1 0 MM IFCH 0 AW 0 MM3 MM2 MM1 MM0 IFCH Internal ROM fetch 0 Fetch at the same speed as from external memory All of the wait control settings are valid 1 High speed fetch The wait control...

Page 440: ...l register 2 PWC2 In the PD784225 Subseries wait cycle insertion control can be performed for the entire address space in one operation using the programmable wait control register 1 PWC1 However in t...

Page 441: ...accessed with priority and the ASTB RD and WD signals are not output remaining at the inactive level The output level of the address bus remains at the previous output level The output of the address...

Page 442: ...n mode 1 MB expansion mode Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Note 2 External memoryNote 1 External memory External memoryNote 2 Inte...

Page 443: ...Single chip mode 256 KB expansion mode 1 MB expansion mode Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Note 2 External memoryNote 1 External m...

Page 444: ...ion mode 1 MB expansion mode Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Note 2 External memoryNote 1 External memoryNote 2 External memory In...

Page 445: ...n Single chip mode 256 KB expansion mode 1 MB expansion mode Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Internal ROM SFR Internal RAM SFR Note 2 External memory External memor...

Page 446: ...ut held at the high level 3 WAIT pin shared by P66 This pin inputs the external wait signal When the external wait is not used WAIT pin can be used as an I O port During an internal memory access the...

Page 447: ...wait cycles PW01 PW00 0 0 ASTB RD AD0 to AD7 A8 to A19 Lower address Instruction code Higher address b Setting 1 wait cycle PW01 PW00 0 1 ASTB RD AD0 to AD7 A8 to A19 Lower address Instruction code H...

Page 448: ...tting 0 wait cycles PW01 PW00 0 0 ASTB RD AD0 to AD7 A8 to A19 Lower address Read data Higher address b Setting 1 wait cycle PW01 PW00 0 1 ASTB RD AD0 to AD7 A8 to A19 Lower address Higher address Int...

Page 449: ...g 0 wait cycles PW01 PW00 0 0 ASTB AD0 to AD7 A8 to A19 Lower address Write data Higher address WR Hi Z b Setting 1 wait cycle PW01 PW00 0 1 ASTB WR AD0 to AD7 A8 to A19 Lower address Write data Highe...

Page 450: ...Higher address Higher address Higher address Lower address Read data Write data WR b Setting 1 wait cycle PW01 PW00 0 1 ASTB AD0 to AD7 A8 to A19 Internal wait signal 1 clock wait RD WR Hi Z Lower add...

Page 451: ...ait is inserted into the entire memory access timeNote When the address wait is inserted the high level period of the ASTB signal is lengthened by one system clock when 80 ns fXX 12 5 MHz Note This ex...

Page 452: ...Figure 23 9 Read Write Timing by Address Wait Function 2 3 b Read timing when an address wait is inserted fXX Note ASTB AD0 to AD7 A8 to A19 Hi Z Hi Z RD Hi Z Lower address Input data Higher address...

Page 453: ...when an address wait is not inserted fXX Note Higher address ASTB AD0 to AD7 A8 to A19 Hi Z Hi Z WR Output data Lower address Hi Z d Write timing when an address wait is inserted fXX Note Higher addr...

Page 454: ...ait control register PWC1 for the 1 MB memory space If an internal ROM or internal RAM is accessed during a high speed fetch a wait is not inserted If accessing an internal SFR a wait is inserted base...

Page 455: ...W01 PW00 0 0 fXX Note Higher address ASTB output AD0 to AD7 A8 to A19 output Hi Z Hi Z RD output Data input Lower address Hi Z b Setting 1 wait cycle PW01 PW00 0 1 fXX Note Higher address ASTB output...

Page 456: ...Figure 23 10 Read Timing by Access Wait Function 2 2 c Setting 2 wait cycles PW01 PW00 1 0 Higher address ASTB output AD0 to AD7 A8 to A19 output Hi Z RD output Data input Lower address Hi Z fXX Note...

Page 457: ...W01 PW00 0 0 fXX Note Higher address ASTB output AD0 to AD7 output A8 to A19 output Hi Z Hi Z WR output Data Lower address Hi Z b Setting 1 wait cycle PW01 PW00 0 1 fXX Note Higher address ASTB output...

Page 458: ...ure 23 11 Write Timing by Access Wait Function 2 2 c Setting 2 wait cycles PW01 PW00 1 0 Higher address ASTB output AD0 to AD7 output A8 to A19 output Hi Z WR output Data Lower address Hi Z fXX Note H...

Page 459: ...Higher address ASTB output AD0 to AD7 A8 to A19 output Hi Z RD output Data input Lower address Hi Z fXX Note WAIT input b Write timing PW01 PW00 1 1 Higher address ASTB output AD0 to AD7 output A8 to...

Page 460: ...n enabled This signal detected the external access status of other devices connected to the external bus prohibits other devices from outputting data to the external bus and enables reception 23 6 2 C...

Page 461: ...ts to 00H Figure 23 14 Format of External Access Status Enable Register EXAE Address 0FF8DH After reset 00H Symbol 7 6 5 4 3 2 1 0 EXAE 0 0 0 0 0 0 0 EXAE0 EXAE P37 function 0 Port function 1 External...

Page 462: ...XA 23 6 5 EXA pin status during each mode P37 EXA pin status during each mode is shown in Table 23 4 Table 23 4 P37 EXA Pin Status in Each Mode Mode P37 EXA Functions After reset Hi Z Normal operation...

Page 463: ...l U12697EJ3V0UM 23 7 External Memory Connection Example Figure 23 15 Example of Local Bus Interface Multiplexed Bus PD784225 RD WR A8 to A19 ASTB AD0 to AD7 VDD1 Address latch LE Q0 to Q7 D0 to D7 OE...

Page 464: ...on near that of the STOP mode and for the same time as the HALT mode Low power consumption mode The subsystem clock is used as the system clock and the main system clock is stopped Since reduced power...

Page 465: ...consumption IDLE mode set RESET input L o w p o w e r c o n s u m p t i o n m o d e s e t R e t u r n t o n o r m a l o p e r a t i o n Low power consumption HALT mode set R E S E T i n p u t Interrup...

Page 466: ...nerated In this case the return address that is saved on the stack is the address of the instruction that caused the error Therefore the address that caused the error can be determined from the return...

Page 467: ...ased 1 1 IDLE mode automatically cleared when the IDLE mode is released Cautions 1 If the STOP mode is used when an external clock is input set the STOP mode after setting bit EXTC in the oscillation...

Page 468: ...ock oscillation frequency fX or fX 2 fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency 2 don t care 2 Clock status register PCS PCS is an 8 bit read only register th...

Page 469: ...k resistor state for subsystem clock 0 Use internal feedback resistors 1 Do not use internal feedback resistors CK2 CK1 CK0 CPU clock operating frequency 0 0 0 fXX 0 0 1 fXX 2 0 1 0 fXX 4 0 1 1 fXX 8...

Page 470: ...0 to OSTS2 in OSTS select the oscillation stabilization time when the STOP mode is released Generally select an oscillation stabilization time of at least 40 ms when using a crystal oscillator and at...

Page 471: ...ms 0 1 1 1 212 fXX 0 4 ms 1 512 fXX 41 0 s Cautions 1 When using crystal ceramic oscillation always clear the EXTC bit to 0 When the EXTC bit is set to 1 oscillation stops 2 If the STOP mode is used w...

Page 472: ...1 specify three NOP instructions after the HALT mode setting instruction after the HALT mode is released If this is not done after the HALT mode is released multiple instructions may execute before i...

Page 473: ...the watch timer 8 bit timer counters 1 2 Operation enabled Operational when TI1 and TI2 are selected as the count clocks 8 bit timer counters 5 6 Operation enabled Operational when TI5 and TI6 are sel...

Page 474: ...ing three sources Non maskable interrupt request Only possible for NMI pin input Maskable interrupt request vectored interrupt context switching macro service RESET input Table 24 3 lists the release...

Page 475: ...level 3 when the PRSL bitNote 4 is cleared to 0 Executing a high priority interrupt service program Operation After Release Normal reset operation Acknowledges interrupt requests The instruction follo...

Page 476: ...e 24 5 Operations After Releasing HALT Mode 1 4 1 Interrupt after HALT mode HALT mode release Interrupt servicing Main routine MOV STBC byte HALT mode Interrupt request 2 Reset after HALT mode Main ro...

Page 477: ...or equal to release source interrupt Main routine HALT mode release HALT mode release source interrupt pending Execution of the pending interrupt HALT mode MOV STBC byte INT 4 HALT mode during interru...

Page 478: ...mode release Servicing of interrupt request due to end of macro service Macro service processing Main routine MOV STBC byte HALT mode Last macro service request b Macro service end condition is not sa...

Page 479: ...nstruction that interrupt requests are temporarily held HALT mode release Interrupt servicing Main routine MOV STBC byte EI Interrupt request Interruption held for the space of eight clocks 7 Contenti...

Page 480: ...kable interrupt request The HALT mode released by a maskable interrupt request can only be released by an interrupt where the interrupt mask flag is 0 If an interrupt can be acknowledged when the halt...

Page 481: ...pt requests The instruction following the MOV STBC byte instruction is executed The interrupt request that released the HALT mode is held pendingNote 3 Holds the HALT mode Macro service process execut...

Page 482: ...the problems caused by changes in the execution order are prevented the measures described earlier are required The system clock during setting can only be set to the main system clock Caution Since a...

Page 483: ...ration disabled the count clock Watchdog timer Operation disabled initializing counter A D converter Operation disabled D A converter Operation enabled Real time output port Operational when an extern...

Page 484: ...pt service program The PRSL bitNote 5 is cleared to 0 while an interrupt service program at priority level 3 is executing Executing a maskable interrupt service program with the same priority This exc...

Page 485: ...STOP Mode 1 3 1 Interrupt after STOP mode Interrupt servicing STOP mode release Main routine MOV STBC byte STOP mode Oscillation stabilization time wait INT 2 Reset after STOP mode Main routine MOV ST...

Page 486: ...outine STOP mode release STOP mode release source interrupt pending Execution of the pending interrupt Oscillation stabilization time wait STOP mode MOV STBC byte INT 4 STOP mode during interrupt serv...

Page 487: ...EJ3V0UM Figure 24 6 Operations After Releasing STOP Mode 3 3 5 Contention between STOP mode setting instruction and interrupt Interrupt servicing STOP mode not executed Main routine MOV STBC byte Exec...

Page 488: ...tion branches to the NMI interrupt service program If acknowledgement is not possible such as when set in the STOP mode in the NMI interrupt service program execution starts again from the instruction...

Page 489: ...rogram If the IE flag is cleared to 0 when acknowledgement is not possible execution starts again from the instruction following the instruction that set the STOP mode For details on interrupt acknowl...

Page 490: ...is set to 1 specify three NOP instructions after the IDLE mode setting instruction after the IDLE mode is released If this is not done after the IDLE mode is released multiple instructions can be exec...

Page 491: ...perational only when fXT is selected as Operation disabled the count clock Watchdog timer Operation disabled A D converter Operation disabled D A converter Operation enabled Real time output port Oper...

Page 492: ...rupt service program The PRSL bitNote 5 is cleared to 0 while executing an interrupt service program at priority level 3 Executing the maskable interrupt service program with the same priority This ex...

Page 493: ...e 24 9 Operations After Releasing IDLE Mode 1 2 1 Interrupt after IDLE mode IDLE mode release Interrupt servicing Main routine MOV STBC byte IDLE mode Interrupt request 2 Reset after IDLE mode Main ro...

Page 494: ...or equal to release source interrupt Main routine IDLE mode release IDLE mode release source interrupt pending Execution of the pending interrupt IDLE mode MOV STBC byte INT 4 IDLE mode during interru...

Page 495: ...al U12697EJ3V0UM Figure 24 9 Operations After Releasing IDLE Mode 3 3 5 Contention between IDLE mode setting instruction and interrupt Interrupt servicing IDLE mode not executed Main routine MOV STBC...

Page 496: ...d and macro service is prohibited and the valid edge specified with external interrupt edge enable register 0 EGP0 EGN0 is input to INTP0 to INTP5 the IDLE mode is canceled At the same time an overflo...

Page 497: ...t consumption of the CMOS IC sometimes increases in this case the CMOS IC overheats and is sometimes destroyed In this case output a suitable level or pull up or pull down resistors The setting method...

Page 498: ...he WAIT pin in the range from the VSS1 voltage to the VDD0 voltage If a voltage outside of this range is applied not only does the current consumption increase but the reliability of the PD784225 is n...

Page 499: ...set 74H in STBC to stop the oscillation of the main system clock Then switch to the backup power supply from the main power supply Note The low power consumption mode is the state where the subsystem...

Page 500: ...aits the oscillation stabilization time of the main system clock and the system clock switches to the main system clock set STBC to 00H Cautions 1 When returning from subsystem clock operation stopped...

Page 501: ...system clock Software wait Execute the instruction that switches to the main system clock Normal operation using the subsystem clock Figure 24 14 Timing for Restoring Main System Clock Operation Main...

Page 502: ...s 1 2 Operational when TI1 and TI2 are selected as the count clocks 8 bit timers 5 and 6 Operational when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fXT is selected...

Page 503: ...2 6Non MaskableInterruptAcknowledgment Operation ii Releasing the HALT mode by a maskable interrupt request An unmasked maskable interrupt request is generated to release the HALT mode When the HALT m...

Page 504: ...al when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fXT is selected as the count clock Watchdog timer Operation disabled A D converter Operation disabled D A convert...

Page 505: ...t and macro service is disabled the oscillator restarts oscillating when a valid edge specified in external interrupt edge enable registers 0 EGP0 EGN0 is input to INTP0 to INTP5 At the same time an o...

Page 506: ...on stabilization 41 9 ms in 12 5 MHz operation the content of the reset vector table is set in the program counter PC Execution branches to the address set in the PC and program execution starts from...

Page 507: ...in system clock oscillator Oscillation stops Oscillation starts Subsystem clock oscillator Not affected by the reset Program counter PC Undefined Set a value in the reset vectored table Stack pointer...

Page 508: ...and fetch and internal ROM s output data is then converted to call command CALLT codes and output when a match is determined When the CALLT command codes are changed to valid commands by the CPU and e...

Page 509: ...RAM 1 byte instruction 3 byte instruction FCH FDH FEH FFH Change of the stack pointer Yes 3 byte save None Address comparison conditions Instruction fetch only Instruction fetch only Correction statu...

Page 510: ...ontrol register ROM correction control register CORC A ROM correction block diagram is shown in Figure 26 1 and Figure 26 2 shows an example of memory mapping Figure 26 1 ROM Correction Block Diagram...

Page 511: ...area Internal ROM Internal high speed RAM Peripheral RAM correction program SFR Internal RAM Internal ROM Reference table 3 Reference table 2 Reference table 1 Reference table 0 CALLT Table area 01FFF...

Page 512: ...isters H and L CORAH CORAL normally compare the corrected address value with the fetch register value If any of the ROM correction control register CORC bits between bit 4 to bit 7 COREN0 to 3 are 1 a...

Page 513: ...COREN0 0 0 CORCH1 0 CORCH0 Address 0FF88H R W After reset 00H Symbol CORENn 0 1 Controls the match detection for the ROM correction address register and the fetch address Disabled Enabled CORCH1 CORC...

Page 514: ...mand that requires correction is read and set in ROM correction address registers H L CORAH CORAL and the correction enable flag COREN0 to 3 is set at 1 A maximum of four locations can be set 3 Execut...

Page 515: ...annel 2 match address MOV CORAH ch2 datah Sets the channel 2 match address MOV CORC 03H Specified channel 3 MOVW CORAL ch3 datah Sets the channel 3 match address MOV CORAH ch3 datal Sets the channel 3...

Page 516: ...78F4225Y Mask ROM versions Internal ROM structure Flash memory Mask ROM Internal ROM capacity 128 KB PD784224 784224Y 96 KB PD784225 784225Y 128 KB Internal RAM capacity 4 352 bytes PD784224 784224Y 3...

Page 517: ...7 1 Format of Internal Memory Size Switching Register IMS IMS 1 7 6 5 4 3 2 1 1 ROM1 ROM0 1 1 RAM1 0 RAM0 Address 0FFFCH W After reset FFH Symbol ROM1 ROM0 1 0 96 KB 128 KB Setting prohibited 1 1 Othe...

Page 518: ...7 3 On Board Overwrite Mode The on board overwrite mode is used with the target system mounted on board Overwriting is performed by connecting a special flash programmer Flashpro III part No FL PR3 PG...

Page 519: ...0 SO0 P26 SI0 P25 SDA0Note 2 SCK1 ASCK1 P22 1 SO1 TxD1 P21 SI1 RxD1 P20 SCK2 ASCK2 P72 2 SO2 TxD2 P71 SI2 RxD2 P70 3 wire serial I O 1 SCK0 P27 SCL0Note 2 3 handshakeNote 3 SO0 P26 SI0 P25 SDA0Note 2...

Page 520: ...state of the specified area Data write Writes to the flash memory based on the start write address and the number of data written the number of bytes Area verify Compares the data input to the content...

Page 521: ...nection diagrams in each case Figure 27 3 Connection of Flashpro III in 3 Wire Serial I O Mode When Using 3 Wire Serial I O 0 Figure 27 4 Connection of Flashpro III in 3 Wire Serial I O Mode When Usin...

Page 522: ...pro III in UART Mode When Using UART1 Note n 1 2 Caution Connect the VPP pin directly to VSS or pull down For the pull down connection use of resistors with a resistance between 470 and 10 k is recomm...

Page 523: ...on register table postNote 2 AX RP0 BC RP1 RP2 RP3 VP RP4 UP RP5 PSW DE RP6 HL RP7 Multiple descriptions are possible However UP is restricted to the PUSH POP instruction and PSW is restricted to the...

Page 524: ...H to FEFDH Immediate data or label when manipulating 24 bits saddrg2 FD20H to FDFFH Immediate data or label when manipulating 24 bits addr24 0H to FFFFFFH Immediate data or label addr20 0H to FFFFFH I...

Page 525: ...ged 0 Clear to zero 1 Set to one Set or clear based on the result P Operate with the P V flag as the parity flag V Operate with the P V flag as the overflow flag R Restore the previously saved value 4...

Page 526: ...s saddr saddrp r or rp in operand The number of bytes in an instruction that has saddr saddrp r or rp in the operand is described in two parts divided by a slash The following table shows the number o...

Page 527: ...1 2 A r A saddr2 2 A saddr2 r saddr 3 r saddr saddr2 A 2 saddr2 A saddr r 3 saddr r A sfr 2 A sfr r sfr 3 r sfr sfr A 2 sfr A sfr r 3 sfr r saddr saddr 4 saddr saddr r addr16 4 r addr16 addr16 r 4 add...

Page 528: ...addr24 word 7 addr24 word rp rp 2 rp rp AX saddrp2 2 AX saddrp2 rp saddrp 3 rp saddrp saddrp2 AX 2 saddrp2 AX saddrp rp 3 saddrp rp AX sfrp 2 AX sfrp rp sfrp 3 rp sfrp sfrp AX 2 sfrp AX sfrp rp 3 sfr...

Page 529: ...g rg saddrg 3 rg saddrg saddrg rg 3 saddrg rg WHL saddrg 3 4 WHL saddrg saddrg WHL 3 4 saddrg WHL WHL mem1 2 5 WHL mem1 mem1 WHL 2 5 mem1 WHL 4 8 bit data exchange instruction XCH Mnemonic Operand Byt...

Page 530: ...R Mnemonic Operand Bytes Operation Flag S Z AC P V CY ADD A byte 2 A CY A byte V r byte 3 r CY r byte V saddr byte 3 4 saddr CY saddr byte V sfr byte 4 sfr CY sfr byte V r r 2 3 r CY r r V A saddr2 2...

Page 531: ...saddr2 CY V r saddr 3 r CY r saddr CY V saddr r 3 saddr CY saddr r CY V r sfr 3 r CY r sfr CY V sfr r 3 sfr CY sfr r CY V saddr saddr 4 saddr CY saddr saddr CY V A saddrp 3 4 A CY A saddrp CY V A sad...

Page 532: ...saddr2 2 A CY A saddr2 V r saddr 3 r CY r saddr V saddr r 3 saddr CY saddr r V r sfr 3 r CY r sfr V sfr r 3 sfr CY sfr r V saddr saddr 4 saddr CY saddr saddr V A saddrp 3 4 A CY A saddrp V A saddrg 3...

Page 533: ...saddr2 CY V r saddr 3 r CY r saddr CY V saddr r 3 saddr CY saddr r CY V r sfr 3 r CY r sfr CY V sfr r 3 sfr CY sfr r CY V saddr saddr 4 saddr CY saddr saddr CY V A saddrp 3 4 A CY A saddrp CY V A sad...

Page 534: ...e V sfr byte 4 sfr byte V r r 2 3 r r V A saddr2 2 A saddr2 V r saddr 3 r saddr V saddr r 3 saddr r V r sfr 3 r sfr V sfr r 3 sfr r V saddr saddr 4 saddr saddr V A saddrp 3 4 A saddrp V A saddrg 3 4 A...

Page 535: ...r r 2 3 r r r P A saddr2 2 A A saddr2 P r saddr 3 r r saddr P saddr r 3 saddr saddr r P r sfr 3 r r sfr P sfr r 3 sfr sfr r P saddr saddr 4 saddr saddr saddr P A saddrp 3 4 A A saddrp P A saddrg 3 4 A...

Page 536: ...r 2 3 r r r P A saddr2 2 A A saddr2 P r saddr 3 r r saddr P saddr r 3 saddr saddr r P r sfr 3 r r sfr P sfr r 3 sfr sfr r P saddr saddr 4 saddr saddr saddr P A saddrp 3 4 A A saddrp P A saddrg 3 4 A A...

Page 537: ...r r 2 3 r r r P A saddr2 2 A A saddr2 P r saddr 3 r r saddr P saddr r 3 saddr saddr r P r sfr 3 r r sfr P sfr r 3 sfr sfr r P saddr saddr 4 saddr saddr saddr P A saddrp 3 4 A A saddrp P A saddrg 3 4 A...

Page 538: ...rp word V saddrp saddrp 4 saddrp CY saddrp saddrp V SUBW AX word 3 AX CY AX word V rp word 4 rp CY rp word V rp rp 2 rp CY rp rp V AX saddrp2 2 AX CY AX saddrp2 V rp saddrp 3 rp CY rp saddrp V saddrp...

Page 539: ...AXr MULUW rp 2 AX high order rp low order AXXrp MULW rp 2 AX high order rp low order AXXrp DIVUW r 2 3 AX quotient r remainder AX rNote 1 DIVUX rp 2 AXDE quotient rp remainder AXDE rpNote 2 Notes 1 Wh...

Page 540: ...V DEC r 1 2 r r 1 V saddr 2 3 saddr saddr 1 V INCW rp 2 1 rp rp 1 saddrp 3 4 saddrp saddrp 1 DECW rp 2 1 rp rp 1 saddrp 3 4 saddrp saddrp 1 INCG rg 2 rg rg 1 DECG rg 2 rg rg 1 12 Decimal adjust instr...

Page 541: ...rp0 0 rpm 1 rpm n n 0 to 7 0 P ROR4 mem3 2 A3 0 mem3 3 0 mem3 7 4 A3 0 mem3 3 0 mem3 7 4 ROL4 mem3 2 A3 0 mem3 7 4 mem3 3 0 A3 0 mem3 7 4 mem3 3 0 14 Bit manipulation instructions MOV1 AND1 OR1 XOR1 N...

Page 542: ...t CY addr16 bit 5 CY CY addr16 bit CY addr24 bit 2 CY CY addr24 bit CY addr24 bit 6 CY CY addr24 bit CY mem2 bit 2 CY CY mem2 bit CY mem2 bit 2 CY CY mem2 bit OR1 CY saddr bit 3 4 CY CY saddr bit CY s...

Page 543: ...r bit X bit 2 X bit X bit A bit 2 A bit A bit PSWL bit 2 PSWL bit PSWL bit PSWH bit 2 PSWH bit PSWH bit addr16 bit 5 addr16 bit addr16 bit addr24 bit 2 addr24 bit addr24 bit mem2 bit 2 mem2 bit mem2 b...

Page 544: ...r SP SP 1 post 2 SP 2 post SP SP 2 mNote rg 2 SP 3 rg SP SP 3 PUSHU post 2 UUP 2 post UUP UUP 2 mNote POP PSW 1 PSW SP SP SP 2 R R R R R sfrp 3 sfrp SP SP SP 2 sfr 3 sfr SP SP SP 1 post 2 post SP SP S...

Page 545: ...r11 2 SP 3 PC 2 SP SP 3 PC19 12 0 PC11 1 PC10 0 addr11 CALLT addr5 1 SP 3 PC 1 SP SP 3 PCHW 0 PCLW addr5 BRK 1 SP 2 PSW SP 1 0 3 PC 1 HW SP 4 PC 1 LW SP SP 4 PCHW 0 PCLW 003EH BRKCS RBn 2 PCLW RP2 RP3...

Page 546: ...J3V0UM 17 Unconditional branch instruction BR Mnemonic Operand Bytes Operation Flag S Z AC P V CY BR addr16 3 PCHW 0 PCLW addr16 addr20 4 PC addr20 rp 2 PCHW 0 PCLW rp rg 2 PC rg rp 2 PCHW 0 PCLW rp r...

Page 547: ...BLT addr20 3 PC PC 3 jdisp8 if P V S 1 BGE addr20 3 PC PC 3 jidsp8 if P V S 0 BLE addr20 3 PC PC 3 jdisp8 if P V S Z 1 BGT addr20 3 PC PC 3 jidsp8 if P V S Z 0 BNH addr20 3 PC PC 3 jdisp8 if Z CY 1 BH...

Page 548: ...jdisp8 if mem2 bit 1 BTCLR saddr bit addr20 4 5 PC PC 4Note 2 jdisp8 saddr bit 0 if saddr bit 1 sfr bit addr20 4 PC PC 4 jdisp8 sfr bit 0 if sfr bit 1 X bit addr20 3 PC PC 3 jdisp8 X bit 0 if X bit 1...

Page 549: ...mem2 bit addr20 3 PC PC 3 jdisp8 mem2 bit 1 if mem2 bit 0 DBNZ B addr20 2 B B 1 PC PC 2 jdisp8 if B 0 C addr20 2 C C 1 PC PC 2 jdisp8 if C 0 saddr addr20 3 4 saddr saddr 1 PC PC 3Note 1 jdisp8 if sadd...

Page 550: ...1 End if C 0 or Z 0 V TDE A 2 TDE A TDE TDE 1 C C 1 End if C 0 or Z 0 V CMPMNE TDE A 2 TDE A TDE TDE 1 C C 1 End if C 0 or Z 1 V TDE A 2 TDE A TDE TDE 1 C C 1 End if C 0 or Z 1 V CMPMC TDE A 2 TDE A T...

Page 551: ...6 ADD Note 1 ADDNote 1 ADDNote 1 ADD Note 1 r MOV MOV MOV MOV MOV MOV RORNote 3 MULU ADDNote 1 XCH XCH XCH XCH XCH DIVUW ADD Note 1 ADDNote 1 ADDNote 1 ADDNote 1 INC DEC saddr MOV MOV Note 6 MOV MOV...

Page 552: ...XCHW ADD Note 1 ADDW Note 1 ADDW Notes 1 3 ADDW Note 1 rp MOVW MOVW MOVW MOVW MOVW MOVW SHRW MULWNote 4 ADDWNote 1 XCHW XCHW XCHW XCHW SHLW INCW ADDW Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 DECW saddr...

Page 553: ...OVG mem1 MOVG saddrg MOVG SP MOVG MOVG INCG DECG Note There is no second operand or the second operand is not an operand address 4 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF...

Page 554: ...structions and Branch Instruction Addressing Instructions Instruction Address Operand addr20 addr20 addr16 addr20 rp rg rp rg addr11 addr5 RBn None Basic instructions BCNote CALL CALL CALL CALL CALL C...

Page 555: ...tion IOE 3 wire serial I O 2 channels CSI 3 wire serial I O 2 wire serial I O SBI 1 channel CSI 3 wire serial I O with automatic communication function 1 channel No No No 2 levels HALT STOP mode Yes 8...

Page 556: ...ws the development tools For PC98 NX series Unless otherwise specified products supported by IBM PC ATTM and compatible machines can be used for the PC98 NX series When using the PC98 NX series refer...

Page 557: ...library source file Device file Debugging tools System simulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC Interface adapter PC card interface etc Flash memory...

Page 558: ...ge C compiler package C library source file Device file Debugging tools System simulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC or EWS Interface board Flash...

Page 559: ...th the assembler package and device file sold separately Caution on using in PC environment Although the C compiler package is a DOS based application it can be used in the Windows environment by usin...

Page 560: ...SolarisTM Rel 2 5 1 1 4 inch CGMT 3R13 NEWSTM RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Also operates in DOS environment B 2 Flash Memory Writing Tools Flashpro III Part No FL PR3 PG FP3 Flash progra...

Page 561: ...the host Interface adapter machine for the IE 78K4 NS IE 784225 NS EM1 Board to emulate the peripheral hardware specific to device Used in combination with Emulation board an in circuit emulator NP 80...

Page 562: ...e IE 784000 R Connect to a board inside the IE 784000 R Note that 10Base 5 is supported as the Ethernet A commercial conversion adapter is required for other systems IE 784000 R EM Emulation board com...

Page 563: ...ce verification can be performed separately to hardware development without using an in circuit emulator thus improving development efficiency and software quality Use the SM78K4 in combination with t...

Page 564: ...bug the 78K IV Series Use these integrated debuggers in combination with the device file DF784225 sold separately Part number S ID78K4 NS S ID78K4 Remark The part number differs depending on the host...

Page 565: ...n pattern Figure B 2 Package Drawing of EV 9200GC 80 Reference Unit mm A F D 1 No 1 pin index E EV 9200GC 80 B C M N O L K S R Q P I H J G EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A B C D E F G H I J...

Page 566: ...236 0 014 0 093 0 091 0 062 0 65 0 02 19 12 35 0 05 0 65 0 02 19 12 35 0 05 0 001 0 002 0 003 0 002 0 001 0 002 0 003 0 002 0 003 0 002 0 003 0 002 0 001 0 001 0 001 0 002 0 001 0 002 Dimensions of m...

Page 567: ...0 062 J 1 2 0 047 E 0 5x19 9 5 0 020x0 748 0 374 F 11 77 0 463 K 7 64 0 301 L 1 2 0 047 M Q 1 2 0 047 R 1 58 0 062 S 3 55 0 140 N 1 58 0 062 O 1 2 P 7 64 0 301 0 047 W 6 8 0 268 X 8 24 0 324 Y 14 8 0...

Page 568: ...number S RX78K4 Caution When purchasing the RX78K IV fill out the purchase application and sign a license Remark The and part numbers varies depending on the host machine and operating system used S...

Page 569: ...part numbers varies depending on the host machine and operating system used S MX78K4 Product Overview Maximum Number Used During Production 001 Evaluation object Use when prototyping XX Manufactured o...

Page 570: ...er 0 CKS 352 353 Clock status register PCS 98 468 469 D D A conversion setting register 0 DACS0 253 D A conversion setting register 1 DACS1 253 D A converter mode register 0 DAM0 254 D A converter mod...

Page 571: ...M12 133 Port 13 P13 132 Port 13 mode register PM13 133 Port function control register 2 PF2 137 Prescaler mode register 0 PRM0 159 Prescaler mode register 1 PRM1 191 Prescaler mode register 2 PRM2 191...

Page 572: ...ddress register 0 SVA0 296 307 Standby control register STBC 95 96 466 467 T Transmission shift register 1 TXS1 263 Transmission shift register 2 TXS2 263 W Watch timer mode control register WTM 221 W...

Page 573: ...M correction address register L 512 CORC ROM correction control register 512 CR00 16 bit capture compare register 00 155 CR01 16 bit capture compare register 01 153 CR10 8 bit compare register 10 187...

Page 574: ...1 Port 1 113 P2 Port 2 114 P3 Port 3 118 P4 Port 4 120 P5 Port 5 122 P6 Port 6 124 P7 Port 7 128 P12 Port 12 131 P13 Port 13 132 PCS Clock status register 98 468 469 PF2 Port function control register...

Page 575: ...Receive shift register 2 263 RXB1 Receive buffer register 1 263 RXB2 Receive buffer register 2 263 S SERIC1 Interrupt control register 369 SERIC2 Interrupt control register 369 SIO0 Serial I O shift...

Page 576: ...register 370 TMIC2 Interrupt control register 370 TMIC5 Interrupt control register 370 TMIC6 Interrupt control register 370 TOC0 16 bit timer output control register 0 157 158 TXS1 Transmission shift...

Page 577: ...ormat of Pull up Resistor Option Register Modification of Figure 6 1 Block Diagram of Real Time Output Port Addition of caution to Figure 6 4 Format of Real Time Output Port Control Register RTPC Modi...

Page 578: ...1 8 bit timer mode control registers 5 and 6 TMC5 TMC6 Modification of Figure 10 2 Format of 8 Bit Timer Mode Control Register 5 TMC5 Modification of Figure 10 3 Format of 8 Bit Timer Mode Control Reg...

Page 579: ...with 1 2 Phase Excitation Modification of Figure 22 38 Automatic Addition Control Ring Control Block Diagram 2 1 2 Phase Excitation Constant Velocity Operation Modification of Figure 22 39 Automatic A...

Page 580: ...H TIMER Modification of Figure 18 17 Communication Reservation Procedure CHAPTER 18 I2C BUS MODE PD784225Y SUBSERIES ONLY Modification of Figure 23 8 Read Modify Write Timing for External Memory CHAPT...

Page 581: ...86 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503...

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