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CHAPTER 24 STANDBY FUNCTION
User’s Manual U12697EJ3V0UM
Table 24-2. Operating States in HALT Mode
HALT Mode Setting
HALT Instruction Mode Setting During
HALT Instruction Mode Setting During
Main System Clock Operation
Subsystem Clock Operation
No subsystem clock
Subsystem clock
When the main system
When the main system
Item
Note 1
Note 2
clock continues oscillating
clock stops oscillating
Clock generator
Both the main system clock and subsystem clock can oscillate.
The clock supply to the CPU stops.
CPU
Operation disabled
Port (output latch)
Holds the state before the HALT mode was set.
16-bit timer/counter
Operation enabled
Operational when the
watch timer output is
selected as the count
clock (Select f
XT
as
the count clock of the
watch timer.)
8-bit timer/counters 1, 2
Operation enabled
Operational when TI1
and TI2 are selected
as the count clocks
8-bit timer/counters 5, 6
Operation enabled
Operational when TI5
and TI6 are selected
as the count clocks
Watch timer
Operational when
Operation enabled
Operational when f
XT
f
XX
/2
7
is selected
is selected as the
as the count clock
count clock
Watchdog timer
Operation disabled (initializing counter)
A/D converter
Operation enabled
Operation disabled
D/A converter
Operation enabled
Real-time output port
Operation enabled
Serial interface
Operation enabled
Operational during
an external SCK.
External interrupt
INTP0 to INTP5 Operation enabled
Bus lines during
AD0 to AD7
High impedance
external expansion A8 to A19
Holds the state before the HALT mode was set.
ASTB
Low level
WR, RD
High level
WAIT
Holds input status
Notes 1.
This includes not supplying the external clock.
2.
This includes supplying the external clock.
