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CHAPTER 24 STANDBY FUNCTION
User’s Manual U12697EJ3V0UM
(2) IDLE mode
(a) Settings and operating states of IDLE mode
When the low power consumption mode is set in the IDLE mode, set 77H in STBC.
Table 24-10 shows the operating states in the IDLE mode.
Table 24-10. Operating States in IDLE Mode
Item
Operating State
Clock generator
The main system clock stops oscillating. The oscillator of the subsystem clock
continues operating. The clock supplied to the CPU and the peripherals stops.
CPU
Operation disabled
Port (output latch)
Holds the state before the IDLE mode was set.
16-bit timer/event counter
Operational when the watch timer output is selected as the count clock
(Select f
XT
as the count clock of the watch timer.)
8-bit timer/event counters 1, 2
Operational when TI1 and TI2 are selected as the count clocks
8-bit timers 5 and 6
Operational when TI5 and TI6 are selected as the count clocks
Watch timer
Operational only when f
XT
is selected as the count clock
Watchdog timer
Operation disabled
A/D converter
Operation disabled
D/A converter
Operation enabled
Real-time output port
Operational when an external trigger is used or TI1 and TI2 are selected as the count
clocks of the 8-bit timer counters 1 and 2
Serial interface
Except I
2
C bus
Operational only when an external input clock is selected as the serial clock
mode
I
2
C bus mode
Operation disabled
External interrupt
INTP0 to INTP5 Operation enabled
Bus lines during
AD0 to AD7
High impedance
external expansion A8 to A19
High impedance
ASTB
High impedance
WR, RD
High impedance
WAIT
Input state is retained.
Caution In the IDLE mode, only external interrupts (INTP0 to INTP5) and watch timer interrupts (INTWT)
can release the IDLE mode and be acknowledged as interrupt requests. All other interrupt
requests are pended, and acknowledged after the IDLE mode has been released through NMI
input, INTP0 to INTP5 input, and INTWT.
