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CHAPTER 25 RESET FUNCTION
User’s Manual U12697EJ3V0UM
Figure 25-2. Receiving Reset Signal
RESET input
Internal reset signal
Internal clock
Analog delay
Analog delay
Analog
delay
Oscillation
stabilization time
Time until clock
starts oscillating
Table 25-1. State After Reset for All Hardware Resets
Hardware
State During Reset (RESET = L)
State After Reset (RESET = H)
Main system clock oscillator
Oscillation stops
Oscillation starts
Subsystem clock oscillator
Not affected by the reset
Program counter (PC)
Undefined
Set a value in the reset vectored table.
Stack pointer (SP)
Undefined
Program status word (PSW)
Initialize to 0000H.
Internal RAM
This is undefined. However, when the standby state is released by a reset, the
value is saved before setting standby.
I/O lines
The input and output buffers turn off.
High impedance
Other hardware
Initialize to the fixed state
Note
.
Note
See
Table 3-6 Special Function Register (SFR) List
when resetting.
