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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U12697EJ3V0UM
3.10 Cautions
(1) Program fetches are not possible from the internal high-speed RAM space (when executing the LOCATION 0H
instruction: 0FD00H to 0FEFFH, when executing the LOCATION 0FH instruction: FFD00H to FFEFFH)
(2) Special function register (SFR)
Do not access an address that is allocated to an SFR in the area from 0FF00H to 0FFFFH
Note
. If mistakenly
accessed, the
µ
PD784225 enters the deadlock state. The deadlock state is released only by reset input.
Note
These addresses are when the LOCATION 0H instruction is executed. They are FFF00H to FFFFFH
when the LOCATION 0FH instruction is executed.
(3) Stack pointer (SP) operation
Although the entire 1 MB space can be accessed by stack addressing, the stack cannot be guaranteed in the
SFR area and the internal ROM area.
(4) Stack pointer (SP) initialization
The SP becomes undefined when RESET is input. Even after a reset is cleared, non-maskable interrupts can
be accepted. Therefore, the SP enters an undefined state immediately after clearing the reset. When a non-
maskable interrupt request is generated, unexpected operations sometimes occur. To minimize these dangers,
always describe the following in the program immediately after clearing a reset.
RSTVCT
CSEG AT 0
DW
RSTSTRT
INITSEG
CSEG BASE
RSTSTRT:
LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
to
