CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
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Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
TP0CE bit = 1
Read TP0OPT0 register
(check overflow flag).
Register initial setting
TP0CTL0 register
(TP0CKS0 to TP0CKS2 bits)
TP0CTL1 register,
TP0IOC1 register,
TP0OPT0 register
Initial setting of these registers
is performed before setting the
TP0CE bit to 1.
The TP0CKS0 to TP0CKS2 bits can
be set at the same time when counting
has been started (TP0CE bit = 1).
START
Execute instruction to clear
TP0OVF bit (CLR TP0OVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TP0CE bit = 0
Counter is initialized and
counting is stopped by
clearing TP0CE bit to 0.
STOP
<3> Count operation stop flow
TP0OVF bit = 1
NO
YES