CHAPTER 13 A/D CONVERTER
User’s Manual U16896EJ2V0UD
377
13.5 Operation
13.5.1 Basic operation
<1> Select the channel whose analog signal is to be converted into a digital signal using the ADS register.
Set the ADM.ADHS1 or ADM.ADHS0 bit.
<2> Set the ADM.ADCS2 bit to 1 and wait 1
μ
s (high-speed mode) or 14
μ
s (normal mode) or longer.
<3> Set the ADM.ADCS bit to 1 to start A/D conversion.
(Steps <4> to <10> are executed by hardware.)
<4> The sample & hold circuit samples the voltage input to the selected analog input channel.
<5> After sampling for a specific time, the sample & hold circuit enters the hold status and holds the input analog
voltage until it has been converted into a digital signal.
<6> Set bit 9 of the successive approximation register (SAR) to 1. The tap selector sets the voltage tap of the
series resistor string to (1/2)
×
AV
REF0
.
<7> The voltage comparator compares the voltage difference between the voltage tap of the series resistor string
and the analog input voltage. If the analog input voltage is greater than (1/2)
×
AV
REF0
, the MSB of the SAR
register remains set to 1. If the analog input voltage is less than (1/2)
×
AV
REF0
, the MSB is cleared to 0.
<8> Next, bit 8 of the SAR register is automatically set to 1 and the next comparison starts. Depending on the
previously determined value of bit 9, the voltage tap of the series resistor string is selected as follows.
•
Bit 9 = 1: (3/4)
×
AV
REF0
•
Bit 9 = 0: (1/4)
×
AV
REF0
The analog input voltage is compared with one of these voltage taps and bit 8 of the SAR register is
manipulated as follows depending on the result of the comparison.
Analog input voltage
≥
voltage tap: Bit 8 = 1
Analog input voltage
≤
voltage tap: Bit 8 = 0
<9> The above steps are repeated until bit 0 of the SAR register has been manipulated.
<10> When comparison of all 10 bits of the SAR register has been completed, the valid digital value remains in the
SAR register, and the value of the SAR register is transferred and latched to the ADCR register.
At the same time, an A/D conversion end interrupt request signal (INTAD) is generated.
<11> Repeat steps <4> to <10> until the ADCS bit is cleared to 0.
For another A/D conversion, start at <3>. However, when operating the A/D converter with the ADCS2 bit
cleared to 0, start at <2>.