CHAPTER 20 RESET FUNCTION
User’s Manual U16896EJ2V0UD
601
20.4.6 Reset operation by clock monitor
If the main clock is monitored using the sampling clock (internal oscillation clock: f
R
) and if it is detected that the
main clock has stopped when the clock monitor operation is enabled, the system is reset and each hardware unit is
initialized to a specific status.
After it is detected that the main clock stops, the system is reset for the duration of a specific time (equivalent to
analog delay), and then the reset status is automatically released. After release of the reset status, the timer for
oscillation stabilization does not perform its counting operation because the main clock is stopped. If watchdog timer
2, which starts by default, overflows, the CPU starts program execution with internal oscillation clock (f
R
).
The status of each hardware unit during the period of reset effected by the CLMRES signal and after release of the
reset status is shown below.
For the timing of reset by the clock monitor, refer to
Figure 21-4
.
Table 20-5. Hardware Status During Reset Operation by Clock Monitor
Item
During Reset
After Reset
Main clock oscillator (f
X
)
Oscillation stops
Oscillation remains stopped
Subclock oscillator (f
XT
) Oscillation
continues
Internal oscillator (f
R
)
Oscillation stops
Oscillation starts
Peripheral clock (f
XX
to f
XX
/1024) Operation
stops
Operation remains stopped because f
X
is
stopped
Internal system clock (f
CLK
) Operation
stops
Operation starts (f
R
) after overflow of
watchdog timer 2
CPU clock (f
CPU
) Operation
stops Operation starts (f
R
) after overflow of
watchdog timer 2
Watchdog timer 1 clock (f
XW
) Operation
stops
Operation remains stopped because f
X
is
stopped
CPU Initialized
Program execution starts after overflow of
watchdog timer 2
Internal RAM
Undefined if writing data to RAM (by CPU) and reset input conflict (data is damaged).
Otherwise value immediately before reset input is retained.
I/O lines (P00)
Low-level output
I/O lines (ports other than P00)
High impedance
On-chip peripheral I/O registers
Initialized to specified status
Watchdog timer 2
Operation stops
Operation starts (f
R
/8 only). However,
WDTRES2 is not generated if watchdog
timer 2 overflows before CPU execution.
Other on-chip peripheral functions Operation
stops
Operation cannot be started because f
X
is
stopped.
However, the peripheral functions that
operate on f
XT
, f
R
, or external clock can
operate (for details, refer to
Table 21-2
).