CHAPTER 21 CLOCK MONITOR
User’s Manual U16896EJ2V0UD
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(c) Operation when main clock is stopped (arbitrary)
If the main clock is stopped by setting the PCC.MCK bit to 1 while the subclock is operating (PCC.CLS bit
= 1), the monitor operation is stopped until the main clock operates (CLS bit = 0). The monitor operation is
automatically started when the main clock starts operating.
Figure 21-3. Operation When Main Clock Is Stopped (Arbitrary)
Clock monitor status
During
monitoring
Monitor stops
Monitor stops
During monitoring
CLME
bit
Internal oscillation
clock
Main clock
CPU operation
Oscillation stops
Subclock operation
Main clock operation
Oscillation stabilization time
(set by OSTS register)
Oscillation stabilization
time counted by software
MCK bit = 1
(d) Operation when CPU operates on internal oscillation clock (CCLS.CCLSF bit = 1)
The monitor operation is not started even if the CLME bit is set to 1 when the CCLSF bit is 1.