CHAPTER 26 FLASH MEMORY
User’s Manual U16896EJ2V0UD
635
Table 26-6. Wiring Between
μ
PD70F3302, 70F3302Y and PG-FP4
Pin Configuration of Flash Programmer (PG-FP4)
With CSI00-HS
With CSI00
With UART0
Signal Name
I/O
Pin Function
Pin Name on
FA Board
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
SI/R
X
D Input
Receive
signal
SI
P41/SO00 20
P41/SO00 20
P30/TXD0 22
SO/T
X
D
Output Transmit
signal
SO
P40/SI00 19
P40/SI00 19
P31/RXD0/
INTP7
23
SCK Output
Transfer
clock
SCK
P42/SCK00 21 P42/SCK00 21 Not
needed Not
needed
X1 X1 7 X1 7 X1 7
CLK Output
Clock
to
V850ES/KE1+
X2
X2
Note
8
X2
Note
8
X2
Note
8
/RESET Output
Reset
signal
/RESET RESET 9
RESET 9
RESET 9
FLMD0 Input Write
voltage
FLMD0 FLMD0 3
FLMD0 3
FLMD0 3
FLMD1 Input
Write
voltage
FLMD1
PDL5/
FLMD1
52
PDL5/
FLMD1
52
PDL5/
FLMD1
52
HS Input
Handshake signal for
CSI00 + HS
communication
RESERVE
/HS
PCM0
45
Not needed Not needed Not needed Not needed
V
DD
4
V
DD
4
V
DD
4
EV
DD
33
EV
DD
33
EV
DD
33
VDD
−
V
DD
voltage
generation/voltage
monitor
VDD
AV
REF0
1
AV
REF0
1
AV
REF0
1
V
SS
6 V
SS
6 V
SS
6
AV
SS
2
AV
SS
2
AV
SS
2
GND
−
Ground
GND
EV
SS
32
EV
SS
32
EV
SS
32
Note
When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its
inverse signal to X2.