1-8 Technical Information
Table 1-2 System Board Feature Components
Chip
Function
Integrated dual-channel enhanced IDE
interface:
•
Supports up to four IDE devices
•
PIO Mode 4 transfers at up to 14 MB/sec
•
Supports Ultra DMA/33 synchronous DMA
mode transfers up to 33 MB/sec
•
Bus master mode with an 8 x 32-bit buffer
for bus master PCI IDE burst transfers
•
Enhanced DMA controller:
•
Two 8237-based DMA controllers
•
Supports PCI DMA with three PC/PCI
channels and distributed DMA protocols
•
Fast type-F DMA for reduced PCI bus
usage
Interrupt controller based on 82C59:
•
Supports 15 interrupts
•
Programmable for edge/level sensitivity
Power management logic:
•
Sleep/resume logic
•
Supports wake-on-modem, Wake on LAN
technology, and wake on PME
Real-Time Clock:
•
256 byte battery-backed CMOS SRAM
•
Includes date alarm
16-bit counters/timers based on 82C54
Intel 82093AA IOAPIC
The IOAPIC provides interrupt management
and incorporates both static and dynamic
symmetric interrupt distribution across all
processors in a multiprocessor system. The
82093AA IOAPIC features 24 interrupts as
follows:
•
13 ISA interrupts
•
Four PCI interrupts
•
One Interrupt/SMI# rerouting