Technical Information 1-15
I/O Addressing
The processor communicates with I/O devices by I/O mapping. The hexadecimal (hex)
addresses of I/O devices are listed in Table 1-4.
NOTE:
In Plug and Play systems, these
addresses are typical but may vary by
configuration.
Table 1-4 I/O Address Map
Address (Hex)
Size
Description
0000 - 000F
16 bytes
PIIX4 - DMA 1
0020 - 0021
2 bytes
PIIX4 - interrupt controller 1
002E - 002F
2 bytes
Super I/O controller configuration registers
0040 - 0043
4 bytes
PIIX4 - Counter/Timer 1
0048 - 004B
4 bytes
PIIX4- Counter/Timer 2
0060
1 byte
Keyboard Controller Byte - Reset IRQ
0061
1 byte
PIIX4 - NMI, Speaker Control
0064
1 byte
Keyboard controller, CMD/STAT Byte
0070, bit 7
1 bit
PIIX4 - enable NMI
0070, bits 6:0
7 bits
PIIX4 - real time clock, address
0071
1 byte
PIIX4 - real time clock, data
0078
1 byte
Reserved - motherboard configuration
0079
1 byte
Reserved - motherboard configuration
0080 - 008F
16 bytes
PIIX4 - DMA page registers
00A0 - 00A1
2 bytes
PIIX4 - interrupt controller 2
00B2 - 00B3
2 bytes
APM control
00C0 - 00DE
31 bytes
PIIX4 - DMA 2
00F0
1 byte
Reset numeric error
0170 - 0177
8 bytes
Secondary IDE channel
01F0 - 01F7
8 bytes
Primary IDE channel
0200 - 0207
8 bytes
Audio / game port
0220 - 022F
16 bytes
Audio (Sound Blaster compatible)
0240 - 024F
16 bytes
Audio (Sound Blaster compatible)
0278 - 027F
8 bytes
LPT2