Operating Precautions for QB-Mini2
Customer Notification
5
(B) Description of Operating Precautions
No.1
Invalid internal high-speed RAM area after RESET
Details
If a RESET signal is generated at the RESET-pin or a RESET occurs due to POC during program
execution, below showed internal high-speed RAM areas become invalid:
-
5 bytes from FECBh to FECFh (When
Permit
is selected in
Target Power OFF
field in the
configuration dialog box)
-
10 bytes from FEC9h to FECFh and FEDDh to FEDFh (When
Not Permit
is selected in
Target Power OFF
field in the configuration dialog box)
Workaround
No workaround available
No.2
Use of watchdog timer
Details
The watchdog timer cannot be used, because it’s forcibly stopped by the debug monitor program.
Don’t set the option byte to disable watchdog timer stop.
Workaround
No workaround available
No.3
Break during sub-clock operation
Details
In the configuration dialog box of the debugger it’s possible to define, if the operating clock during a
break is switched from sub-clock to main clock. But if UART is the communication channel
between QB-MINI2-EE and target device, an occurring break during sub-clock operation (while the
main clock has been stopped) will forcibly switch the operation clock to main clock. The device
continues its operation with the main clock after monitor program execution.
Workaround
No workaround available
No.4
Break during flash memory modifications
Details
A break may occurs at an unexpected address during flash memory modifications (for example
usage of flash self-programming libraries).
Workaround
Reset the device and repeat program execution.
