820
Chapter 18
AFCAN Controller
User’s Manual U16580EE3V1UD00
the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not
resume transmission from the message buffer where ABT stopped, the internal ABT engine can be
reset by setting the ABTCLR bit to 1 while ABT mode is stopped and the ABTTRG bit is cleared to 0. In
this case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the
ABTTRG bit is set to 1.
An interrupt can be used to check if data frames have been transmitted from all the message buffers for
ABT. To do so, the IE bit of the CnMCTRLm register of each message buffer except the last message
buffer needs to be cleared (0).
If a transmit message buffer other than those used by the ABT function (message buffers 8 to 31) is
assigned to a transmit message buffer, the message to be transmitted next is determined by the priority
of the transmission ID of the ABT message buffer whose transmission is currently held pending and the
transmission ID of the message buffers other than those used by the ABT function.
Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list
(THL).
Cautions: 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume
ABT operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is
set to 1, the subsequent operation is not guaranteed.
2. If the automatic block transmission engine is cleared by setting the ABTCLR bit
to 1, the ABTCLR bit is automatically cleared immediately after the processing of
the clearing request is completed.
3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in
the initialization mode, the proper operation is not guaranteed after the mode is
changed from the initialization mode to the ABT mode.
4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal
operation mode with ABT. Otherwise, the operation is not guaranteed.
5. The CnGMABTD register is used to set the delay time that is inserted in the
period from completion of the preceding ABT message to setting of the TRQ bit
for the next ABT message when the transmission requests are set in the order of
message numbers for each message for ABT that is successively transmitted in
the ABT mode. The timing at which the messages are actually transmitted onto
the CAN bus varies depending on the status of transmission from other stations
and the status of the setting of the transmission request for messages other than
the ABT messages (message buffers 8 to 31).
6. If a transmission request is made for a message other than an ABT message and
if no delay time is inserted in the interval in which transmission requests for ABT
are automatically set (CnGMABTD register = 00H), messages other than ABT
messages may be transmitted not depending on their priority compared to the
priority of the ABT message.
7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1.
8. If a message is received from another node while normal operation mode with
ABT is active, the TX-message from the ABT-area may be transmitted with delay
of one frame although CnGMABTD register was set up with 00H.
18.10.4 Transmission abort process
(1)
Transmission abort process except for in normal operation mode with automatic block
transmission (ABT)
The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request.
The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission
was successfully aborted or not can be checked using the TSTAT bit of the CnCTRL register and
the CnTGPT register, which indicate the transmission status on the CAN bus (for details, refer to
the processing in <~Reference>Figure 18-45 on page 850).
Summary of Contents for V850E/PH2
Page 6: ...6 Preface User s Manual U16580EE3V1UD00...
Page 16: ...16 User s Manual U16580EE3V1UD00...
Page 28: ...28 User s Manual U16580EE3V1UD00...
Page 32: ...32 User s Manual U16580EE3V1UD00...
Page 84: ...84 Chapter 2 Pin Functions User s Manual U16580EE3V1UD00 MEMO...
Page 144: ...144 Chapter 3 CPU Functions User s Manual U16580EE3V1UD00 MEMO...
Page 192: ...192 Chapter 5 Memory Access Control Function PD70F3187 only User s Manual U16580EE3V1UD00 MEMO...
Page 312: ...312 Chapter 9 16 Bit Timer Event Counter P User s Manual U16580EE3V1UD00 MEMO...
Page 534: ...534 Chapter 11 16 bit Timer Event Counter T User s Manual U16580EE3V1UD00...
Page 969: ...969 Chapter 20 Port Functions User s Manual U16580EE3V1UD00 MEMO...
Page 970: ...970 Chapter 20 Port Functions User s Manual U16580EE3V1UD00...
Page 976: ...976 Chapter 22 Internal RAM Parity Check Function User s Manual U16580EE3V1UD00 MEMO...
Page 984: ...984 Chapter 23 On Chip Debug Function OCD User s Manual U16580EE3V1UD00 MEMO...
Page 1006: ...1006 Chapter 24 Flash Memory User s Manual U16580EE3V1UD00 MEMO...
Page 1036: ...1036 Chapter 27 Recommended Soldering Conditions User s Manual U16580EE3V1UD00 MEMO...
Page 1046: ...1046 Appendix A Index User s Manual U16580EE3V1UD00 MEMO...
Page 1052: ...1052 User s Manual U16580EE3V1UD00...
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