Hardware Functional Overview 3-5
Flash ROM Boot block erase protection
Supports three general purpose I/O
Hybrid Voltage
208 Pins QFP
n
Integration
Built-in 206
Built-in 146818A
Built-in Memory Controller
Built-in VESA Bus Controller
n
Memory Controller
Supports ROM DOS up to 64MB by XIP, 16MB by EMS
Supports Shadow RAM from C0000-FFFFF
Supports SLOW and SELF Refresh DRAM
Supports Stagger Refresh
On-board memory up to 48MB
Supports Three Memory Banks
Supports Page Mode/Burst mode operation
Supports 512KBx8, 1Mx4, 1Mx16, 2Mx8 and 4Mx4 type DRAM
Supports 8 or 16 bit ROM configuration
Programmable DRAM timing for each bank
n
Power Management
Supports up to Ten Programmable PMC Outputs
Supports Multiple Power Saving Modes
Full On Mode
ON Mode
DOZE Mode
Summary of Contents for VERSA 500D WINDOWS 98 - UPGRADE INFORMATION
Page 79: ...4 8 Field Service Guidelines ...
Page 127: ...Index 3 ...
