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36
NDiS B537 Series User Manual
Appendix A: Watchdog Timer
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PPendIx
a: W
atChdog
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Imer
The NDiS B537 series features a watchdog timer that resets the CPU or
generates an interrupt if the processor stops operating for any reason. This
feature ensures system reliability in industrial standalone or unmanned
environments.
Watchdog Timer Control Register (Index=71h, Default=00h)
Bit
Description
7
WDT is reset upon a CIR interrupt.
6
WDT is reset upon a KBC (Mouse) interrupt.
5
WDT is reset upon a KBC (Keyboard) interrupt.
4
Reserved
3-2
Reserved
1
Force Time-out
This bit is self-cleared.
0
WDT Status
1: WDT value is equal to 0.
0: WDT value is not equal to 0.
Watchdog Timer Configuration Register (Index=72h, Default=001s0000b)
Bit
Description
7
WDT Time-out Value Select 1
1: Second
0: Minute
6
WDT Output through KRST (pulse) Enable
1: Enable
0: Disable
5
WDT Time-out Value Extra Select
1: 64ms x WDT Timer-out value (default = 4s)
0: Determined by WDT Time-out value select 1 (bit 7 of this register)
4
WDT Output through PWRGD Enable
1: Enable
0: Disable
During LRESET# this bit is selected by JP2 power-on strapping option.
3-0
Interrupt Level Select for WDT
Please refer to Interrupt Level Mapping Table.
Watchdog Timer Time-out Value (LSB) Register (Index=73h, Default=38h)
Bit
Description
7-0
WDT Time-out Value 7-0
Watchdog Timer Time-out Value (MSB) Register (Index=74h, Default=00h)
Bit
Description
7-0
WDT Time-out Value 15-8
