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37
NDiS B537 Series User Manual
Appendix A: Watchdog Timer
SMI# Control Register 2 (Index=F1h, Default=00h)
Bit
Description
7
Reserved
6
0: Edge trigger
1: Level trigger
5-3
Reserved
2
This bit enables the generation of a SMI# due to WDT’s IRQ (EN_WDT).
1
This bit enables the generation of a SMI# due to CIR’s IRQ (EN_CIR).
0
This bit enables the generation of a SMI# due to PBD’s IRQ (EN_PBD).