Glossary
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National Instruments Corporation
G-3
P
parity
Method of error checking. Ensures that there is always either an even
number or an odd number of asserted bits in a byte, character, or word,
according to the logic of the system. If a bit should be lost in data
transmission, its loss can be detected by checking the parity
PCI
Peripheral Component Interconnect. A high-performance expansion bus
architecture originally developed by Intel to replace ISA and EISA. PCI
offers a theoretical maximum transfer rate of 133 Mbytes/s.
PCIe
PCI express. A high-performance expansion bus architecture originally
developed by Intel to replace PCI. PCIe offers a theoretical maximum
transfer rate that is dependent upon lane width. A x1 link theoretically
provides 250 MB/s in each direction to and from the device. Once overhead
is accounted for, a x1 link can provide up to 200 MB/s of input capability
and 200 MB/s of output capability. Increasing the number of lanes in a link
increases maximum throughput by approximately the same factor.
pixel
Picture element. The smallest division that makes up the video scan line;
for display on a computer monitor, a pixel’s optimum dimension is square
(aspect ratio of 1:1, or the width equal to the height).
pixel clock
Divides the incoming horizontal video line into pixels.
protocol
The exact sequence of bits, characters, and control codes used to transfer
data between computers and peripherals through a communications
channel.
Q
quadrature encoder
A device that converts angular rotation into two pulse trains, A and B.
The phase difference between A and B transmits information about the
direction of rotation and the number of transitions indicates the amount of
rotation.
R
real time
A property of an event or system in which data is processed as it is acquired
instead of being accumulated and processed at a later time.
