Chapter 3
Hardware Overview
3-10
ni.com
Figure 3-3.
High-Level Schematic of NI 6653 Signal Routing Architecture
Figure 3-4 provides a more detailed view of the
Selection Circuitry
referenced in Figure 3-3.
Figure 3-4.
Signal Selection Circuitry Diagram
PFI 0
DDS
PXI_CLK10
÷2
N
÷2
M
PFI 0
DDS
PXI_CLK10
÷2
N
÷2
M
Selection
Circuitry
Selection
Circuitry
PFI 0
PFI 1
PFI 5
Selection
Circuitry
Selection
Circuitry
PXI_STAR 0
PXI_STAR 1
PXI_STAR 12
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
PXI_TRIG 0
PXI_TRIG 1
PXI_TRIG 7
Selection
Circuitry
Selection
Circuitry
3
SYNCHRONIZATION
CLOCKS for PFI<0..5>
28
SOURCE
*
3
*
PXI_STAR<0..12>,
PXI_TRIG<0..7>,
PFI<0..5>, and
Software Trigger are
routed to SOURCE
of each Selection
Circuitry block.
SYNCHRONIZATION
CLOCKS for
PXI_STAR<0..12> and
PXI_TRIG<0..7>
PFI<0..5>
PXI_TRIG<0..7>
PXI_STAR<0..12>
Software Trigger
GND
CLK
CLK/N
CLK/M
SYNCHR
ONIZA
TION
CLOCKS
SOURCE
DESTINA
TION