NIP
Pollux GigE Series – 01M / 05M Camera
Page
42
of
56 Manual 1.0
4.10
I/O Electric Feature
4.10.1
Line0 Opto-isolated Input Circuit
In controlling camera I/O, Line0 input circuit can be shown in Figure 54.
Figure 54.
Input Circuit
Logic 0 input level: 0~1VDC (OPTO_IN pin)
Logic 1 input level: 1.5~24VDC (OPTO_IN pin)
Maximum input current: 25 mA
Please make sure the input voltage is not from 1V to 1.5V as the electric status
among the two values is not stable.
Figure 55.
Input Logic Level
Input rising delay (TDR): 2.6μs
Input falling delay (TDF): 19.2μs