ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 142 -
Revision 2.4
GPIO Port [A/B] Interrupt Mode Control (Px _INTTYPE)
Register
Offset
R/W
Description
Reset Value
PA_INTTYPE
0x018 R/W
GPIO Port A Interrupt Trigger Type
0xXXXX_0000
PB_INTTYPE
0x058 R/W
GPIO Port B Interrupt Trigger Type
0xXXXX_0000
Table 5-55 GPIO Interrupt Mode Control (Px_INTTYPE)
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
TYPE[15:8]
7
6
5
4
3
2
1
0
TYPE[7:0]
Bits
Description
[31:16]
Reserved
Reserved.
[15:0]
TYPE
Port [A/B] Edge or Level Detection Interrupt Trigger Type
TYPE[n] used to control whether the interrupt mode is level triggered or edge
triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by
the DBEN register. If the interrupt mode is level triggered, the input source is
sampled each clock to generate an interrupt
0 = Edge triggered interrupt.
1 = Level triggered interrupt.
If level triggered interrupt is selected, then only one level can be selected in the
Px_INTEN register. If both levels are set no interrupt will occur
