ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 309 -
Revision 2.4
Time Out Register (UARTn_TOUT)
Register
Offset
R/W
Description
Reset Value
UARTn_TOUT
U0x20 R/W
UART Time Out Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
TOIC
Table 5-127 UART Time Out Register (UARTn_TOUT, address 0x4005_0020)
Bits
Description
[31:7]
Reserved
Reserved.
[6:0]
TOIC
Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a
new data word. Once the content of time out counter is equal to that of time out
interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if
UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears
RXTOIF. The period of the time out counter is the baud rate.