ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 386 -
Revision 2.4
A/D Compare Register 0 (
SDADC_CMPR0
)
Register
Offset
R/W
Description
Reset Value
SDADC_CMPR0
S0x18 R/W
SD ADC Comparator 0 Control Register
0x0000_0000
31
30
29
28
27
26
25
24
CMPOEN
CMPD
23
22
21
20
19
18
17
16
CMPD
15
14
13
12
11
10
9
8
CMPD
7
6
5
4
3
2
1
0
CMPMATCNT
CMPF
CMPCOND
CMPIE
Reserved
Bits
Description
[31]
CMPOEN
Compare Match output FIFO zero
1 = compare match then FIFO out zero
0 = FIFO data keep original one.
[30:8]
CMPD
Comparison Data
23 bit value to compare to FIFO output word.
[7:4]
CMPMATCNT
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the
internal match counter will increase by 1. When the internal counter reaches the value
to (CMP1), the CMPF bit will be set.
[3]
CMPF
Compare Flag
When the conversion result meets condition in CMPCOND and CMPMATCNT this bit
is set to 1. It is cleared by writing 1 to self.
[2]
CMPCOND
Compare Condition
1= Set the compare condition that result is greater or equal to CMPD
0= Set the compare condition that result is less than CMPD
Note:
When the internal counter reaches the value (CMP1), the CMPF bit
will be set.
[1]
CMPIE
Compare Interrupt Enable
1 = Enable compare function interrupt.
0 = Disable compare function interrupt.
If the compare function is enabled and the compare condition matches the setting of
CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a
compare interrupt request is generated.
[0]
Reserved
Reserved.
