ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.2.7
Nested Vectored Interrupt Controller (NVIC)
Cortex-M0 includes an interrupt controller the “Nested Vectored Interrupt Controller (NVIC)”. It is
closely coupled to the processor kernel and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority changing
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ [31:0]) discrete interrupts with 4 levels of priority. All
of the interrupts and most of the system exceptions can be configured to different priority levels. When
an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When any interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and branch
to the starting address of the corresponding ISR by software. While the starting address is fetched,
NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12”
to the stack. At the end of the ISR, the NVIC will restore the above mentioned registers from the stack
and resume normal execution. This provides a high speed and deterministic time to process any
interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of state saving and restoration and therefore reduces delay time in switching to a pending
ISR at the end of the current ISR. The NVIC also supports “Late Arrival” which improves the efficiency
of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to
execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the
higher one without delay penalty. This aids real-time, high priority, interrupt capability.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”
.
5.2.7.1
Exception Model and System Interrupt Map
The following table lists the exception model supported by ISD91200 series. Software can set four
levels of priority on certain exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-
configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after
three system exceptions “Reset”, “NMI” and “Hard Fault”.
