ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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AHB Bus Matrix Priority Control Register (AHBMCTL)
Register
Offset
R/W Description
Reset Value
AHBMCTL
0x40000400
R/W AHB Bus Matrix Priority Control Register
0x0000_0001
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
INTACTEN
Bits
Description
[31:1]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[0]
INTACTEN
Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protected)
Enable Cortex
®
-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix
0 = Round-robin mode.
1 = Cortex
®
-M4 CPU with highest bus priority when interrupt occur.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
