ISD94100 Series Technical Reference Manual
Sep 9, 2019
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AHB Devices Clock Enable Control Register (CLK_AHBCLK)
The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock.
Register
Offset
R/W Description
Reset Value
CLK_AHBCLK
0x04
R/W AHB Devices Clock Enable Control Register
0x0000_8004
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
FMCIDLE
Reserved
7
6
5
4
3
2
1
0
CRCCKEN
Reserved
ISPCKEN
PDMACKEN
Reserved
Bits
Description
[31:16]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[15]
FMCIDLE
Flash Memory Controller Clock Enable Bit in IDLE Mode
0 = FMC clock Disabled when chip is under IDLE mode.
1 = FMC clock Enabled when chip is under IDLE mode.
[14:8]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[7]
CRCCKEN
CRC Generator Controller Clock Enable Bit
0 = CRC peripheral clock Disabled.
1 = CRC peripheral clock Enabled.
[6:3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2]
ISPCKEN
Flash ISP Controller Clock Enable Bit
0 = Flash ISP peripheral clock Disabled.
1 = Flash ISP peripheral clock Enabled.
[1]
PDMACKEN
PDMA Controller Clock Enable Bit
0 = PDMA peripheral clock Disabled.
1 = PDMA peripheral clock Enabled.
[0]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
