ISD94100 Series Technical Reference Manual
Sep 9, 2019
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APB Devices Clock Enable Control Register 1
(CLK_APBCLK1)
The bits in this register are used to enable/disable clock for peripheral controller clocks.
Register
Offset
R/W Description
Reset Value
CLK_APBCLK1
0x0C
R/W APB Devices Clock Enable Control Register 1
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
PWM0CKEN
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
DPWMCKEN
Reserved
Bits
Description
[31:17]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[16]
PWM0CKEN
PWM0 Clock Enable Bit
0 = PWM0 clock Disabled.
1 = PWM0 clock Enabled.
[15:7]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[6]
DPWMCKEN
DPWM Clock Enable Bit
0 = DPWM clock Disabled.
1 = DPWM clock Enabled.
[5:0]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
