ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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Power Manager Control Register
(CLK_PMUCTL)
Register
Offset
R/W Description
Reset Value
CLK_PMUCTL
0x90
R/W Power Manager Control Register
0x0000_0080
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
RTCWKEN
Reserved
BODSPWK
Reserved
WKPINEN
15
14
13
12
11
10
9
8
Reserved
WKTMRIS
WKTMREN
7
6
5
4
3
2
1
0
Reserved
PDMSEL
Bits
Description
[31:24]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[23]
RTCWKEN
RTC Wake-up Enable Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
0 = RTC wake-up disable at Standby Power-down mode.
1 = RTC wake-up enabled at Standby Power-down mode.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[22:20]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[19]
BODSPWK
BOD Standby Power-down Mode Wake-up Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
0 = BOD wake-up disable at Standby Power-down mode.
1 = BOD wake-up enabled at Standby Power-down mode.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[18]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[17:16]
WKPINEN
Wake-up Pin Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
00 = Wake-up pin disable at Deep Power-down mode.
01 = Wake-up pin rising edge enabled at Deep Power-down mode.
10 = Wake-up pin falling edge enabled at Deep Power-down mode.
11 = Wake-up pin both edge enabled at Deep Power-down mode.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[15:12]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
