ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Standby Power-down Wake-up De-bounce Control Register
(CLK_SWKDBCTL)
Register
Offset
R/W Description
Reset Value
CLK_SWKDBCTL
0x9C
R/W
Standby Power-down Wake-up De-bounce Control
Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
SWKDBCLKSEL
Bits
Description
[31:4]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[3:0]
SWKDBCLKSEL
Standby Power-down Wake-up De-bounce Sampling Cycle Selection
0000 = Sample wake-up input once per 1 clocks.
0001 = Sample wake-up input once per 2 clocks.
0010 = Sample wake-up input once per 4 clocks.
0011 = Sample wake-up input once per 8 clocks.
0100 = Sample wake-up input once per 16 clocks.
0101 = Sample wake-up input once per 32 clocks.
0110 = Sample wake-up input once per 64 clocks.
0111 = Sample wake-up input once per 128 clocks.
1000 = Sample wake-up input once per 256 clocks.
1001 = Sample wake-up input once per 2*256 clocks.
1010 = Sample wake-up input once per 4*256 clocks.
1011 = Sample wake-up input once per 8*256 clocks.
1100 = Sample wake-up input once per 16*256 clocks.
1101 = Sample wake-up input once per 32*256 clocks.
1110 = Sample wake-up input once per 64*256 clocks.
1111 = Sample wake-up input once per 128*256 clocks.
.
Note:
De-bounce counter clock source is the internal low speed RC oscillator (LIRC).
