ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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Supports PDMA transfer.
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Supports up to four channel digital microphones.
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Both digital PDM microphone inputs can be used simultaneously.
Voice Active Detection
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Configuration detect levels.
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Supports idle mode wake-up function.
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Supports auto switch DMIC path when CPU wake-up by VAD.
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Generates interrupt requests when voice detected.
Audio DPWM Modulator
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Differential Audio PWM Output (DPWM)
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Supports left channel, right channels and sub-woofer channel.
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Supports sample rate from 16~96 kHz
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Programmable biquad filter with 10 band.
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PDMA data channel for streaming of PCM audio data.
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Supports the single precision floating point for input data and BIQ coefficient.
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Provides one 32-level FIFO data buffers for transmitting.
Cyclic Redundancy Calculation Unit
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Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
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Programmable initial value
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Supports programmable order reverse setting for input data and CRC checksum
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Supports programmable 1’s complement setting for input data and CRC checksum.
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Supports 8-/16-/32-bit of data width
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Programmable seed value
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8-bit write mode: 1-AHB clock cycle operation
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16-bit write mode: 2-AHB clock cycle operation
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32-bit write mode: 4-AHB clock cycle operation
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Supports using DMA to write data to perform CRC operation
Brown-out Detector
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With 8 levels: 3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V
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Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 1.5V
Operating Temperature: -40
℃
~85
℃
Packages
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All Green package (RoHS)
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QFN 48-pin (6x6 mm)
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LQFP 64-pin (7x7 mm)
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LQFP 64-pin (10x10 mm)
