ISD94100 Series Technical Reference Manual
Sep 9, 2019
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6.6 PDMA Controller (PDMA)
6.6.1
Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other
applications. The PDMA controller has a total of 16 channels and each channel can perform transfer
between memory and peripherals or between memory and memory.
6.6.2
Features
Supports 16 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word
or no increment
Supports software and SPI, UART, ADC and PWM
request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of
the descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
6.6.3
Block Diagram
The block diagram about PDMA controller is shown as follows.
AHB
PDMA Controller
Embedded SRAM
Ch0 DSCT
Ch15 DSCT
Peripheral
Descriptor Table
(DSCT)
ack
finish
Peripheral
n
CH15
Control
CH0
Control
Master / Slave Wrapper
I/O, Decoder
Registers
Bus Master
Control
req
ack
finish
Peripheral
0
req
ack
finish
Peripheral
1
req
Peripheral Interface
Control
Figure 6.6-1 PDMA Controller Block Diagram
