ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
DIRF
(PWM_CNTn[16])
0
1
2
3
4
3
1
2
0
1
2
3
4
3
1
2
0
5
6
7
6
4
5
1
2
3
4
PWM Period
PERIOD = 4
PERIOD = 7
PWM Period
zero point event
center point event
CNT
(PWM_CNTn[15:0])
CNTENn
(PWM_CNTEN[n])
Note1:
When in up-down count type, period interrupt flag occurs at center point event.
Note2:
n denotes channel 0,1..5
X
Figure 6.8-10 PWM Up-Down Counter Type
6.8.5.6
PWM Comparator
There are two kinds of comparator registers : one is CMPDATn(n = 0,1..5), and the other is
FTCMPDATn_m(n = 0,2,4, m = 1,3,5) register. CMPDATn is a basic comparator register of PWM
channel n; In Independent mode each channel only has one comparator, the value of CMPDATn
register is continuously compared to the corresponding channel’s counter value. In Complementary
mode each paired channels has two comparators, and the value of CMPDATn and CMPDATm (n
= 0,2,4, m = 1,3,5) registers are continuously compared to the complementary even channel’s
counter value, because of odd channel’s counter is useless. For example, channel 0 and channel
1 are complementary channels, in Complementary mode, channel 1’s comparator is continuously
compared to channel 0’s counter, but not channel 1’s. When the counter is equal to value of
CMPDAT0 register, PWM generates a compared point event and uses the event to generate PWM
pulse, interrupt or use to trigger EADC. In up-down counter type, two events will be generated in a
PWM period as shown in Figure 6.8-11. The CMPU is up count compared point event and CMPD
is down count compared point event.
