ISD94100 Series Technical Reference Manual
Sep 9, 2019
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CNT
Edge Detect
Brake Source
PWM_CH0
PWM_CH0 signals resume at next start
of PWM period after BRKEIF0 clear
BRKEIF1
BRKEIF0
s/w clear
BRKESTS0
BRKESTS1
s/w clear
PWM_CH1
PWM_CH1 signals resume at next start
of PWM period after BRKEIF1 clear
Note:
Output Brake State
Setting: BRKAEVEN = 3 (High)
BRKAODD = 2 (Low)
Figure 6.8-32 Edge Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair
CNT
Level Detect
Brake Source
PWM_CH0
BRKLIF1
BRKLIF0
s/w clear
BRKLSTS0
BRKLSTS1
s/w clear
PWM_CH1
No matter BRKLIF0 or BRKLIF1 clear or not, while no brake
event occur, brake state resume at next start of PWM period
Note:
Output Brake State
Setting: BRKAEVEN = 3 (High)
BRKAODD = 2 (Low)
Figure 6.8-33 Level Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair
The two kinds of detectors detect the same five brake sources: two from external input signals, one
from ADC result monitor (EADCRM), one from system fail and one from software triggered, that are
