ISD94100 Series Technical Reference Manual
Sep 9, 2019
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6.10.4 Basic Configuration
Clock source configuration
–
Select the source of WWDT peripheral clock in WWDTSEL (CLK_CLKSEL1[31:30])
–
Enable WWDT peripheral clock in WDTCKEN (CLK_APBCLK0[0]).
The WWDT clock control are shown in Figure 6.10-2.
10
HCLK/2048
WDTCKEN (CLK_APBCLK0[0])
WWDT_CLK
11
10 kHz (LIRC)
WWDTSEL (CLK_CLKSEL1[31:30])
Figure 6.10-2 WWDT Clock Control
6.10.5 Functional Description
The WWDT includes a 6-bit down counter with programmable prescale value to define different
WWDT time-out intervals. The clock source of 6-bit WWDT is based on system clock divide 2048
(HCLK/2048) or 10 kHz internal low speed RC oscillator (LIRC) with a programmable 11-bit
prescale counter value which controlled by PSCSEL (WWDT_CTL[11:8]). Also, the correlate of
PSCSEL (WWDT_CTL[11:8]) and prescale value are listed in the Table 6.10.5-1.
PSCSEL
Prescaler Value
Max. Time-Out Period
Max. Time-Out Interval
(WWDT_CLK=10 KHz)
0000
1
1 * 64 * T
WWDT
6.4 ms
0001
2
2 * 64 * T
WWDT
12.8 ms
0010
4
4 * 64 * T
WWDT
25.6 ms
0011
8
8 * 64 * T
WWDT
51.2 ms
0100
16
16 * 64 * T
WWDT
102.4 ms
0101
32
32 * 64 * T
WWDT
204.8 ms
0110
64
64 * 64 * T
WWDT
409.6 ms
0111
128
128 * 64 * T
WWDT
819.2 ms
1000
192
192 * 64 * T
WWDT
1.2288 s
1001
256
256 * 64 * T
WWDT
1.6384 s
1010
384
384 * 64 * T
WWDT
2.4576 s
1011
512
512 * 64 * T
WWDT
3.2768 s
