ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
581
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
auto-flow control that provides programmable nRTS flow control trigger level. The number of data
bytes in RX FIFO is equal to or greater than RTSTRGLV (UART_FIFO[19:16]), the nRTS is de-
asserted.
UART Line Control Function
The UART controller supports fully programmable serial-interface characteristics via UART_LINE
register. Table 6.12.5-7 and Table 6.12.5-8 provide a quick reference for UART port format setting.
NSB
(UART_LINE[2])
WLS
(UART_LINE[1:0])
Word Length (Bit)
Stop Length (Bit)
0
00
5
1
0
01
6
1
0
10
7
1
0
11
8
1
1
00
5
1.5
1
01
6
2
1
10
7
2
1
11
8
2
Table 6.12.5-7 UART Line Control of Word and Stop Length Setting
Parity Type
SPE
(UART_LINE[5])
EPE
(UART_LINE[4])
PSS
(UART_LINE[7])
PBE
(UART_LINE[3])
Description
No Parity
x
x
x
0
No parity bit output.
Parity source
from UART_DAT
x
x
1
1
Parity bit is generated and checked
by software.
Odd Parity
0
0
0
1
Odd Parity is calculated by adding all
the “1’s” in a data stream and adding
a parity bit to the total bits, to make
the total count an odd number.
Even Parity
0
1
0
1
Even Parity is calculated by adding
all the “1’s” in a data stream and
adding a parity bit to the total bits, to
make the count an even number.
Forced Mask
Parity
1
0
0
1
Parity bit always logic 1.
Parity bit on the serial byte is set to
“1” regardless of total number of “1’s”
(even or odd counts).
Forced Space
Parity
1
1
0
1
Parity bit always logic 0.
Parity bit on the serial byte is set to
“0” regardless of total number of “1’s”
(even or odd counts).
Table 6.12.5-8 UART Line Control of Parity Bit Setting
